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Searched
defs:RCI
(Results
1 - 13
of
13
) sorted by null
/external/swiftshader/third_party/LLVM/lib/CodeGen/
AllocationOrder.h
29
const RegisterClassInfo &
RCI
;
RegisterClassInfo.cpp
71
RCInfo &
RCI
= RegClass[RC->getID()];
76
if (!
RCI
.Order)
77
RCI
.Order.reset(new unsigned[NumRegs]);
94
RCI
.Order[N++] = PhysReg;
96
RCI
.NumRegs = N + CSRAlias.size();
97
assert (
RCI
.NumRegs <= NumRegs && "Allocation order larger than regclass");
100
std::copy(CSRAlias.begin(), CSRAlias.end(), &
RCI
.Order[N]);
104
if (Super != RC && getNumAllocatableRegs(Super) >
RCI
.NumRegs)
105
RCI
.ProperSubClass = true;
109
for (unsigned I = 0; I !=
RCI
.NumRegs; ++I
[
all
...]
RegisterClassInfo.h
65
const RCInfo &
RCI
= RegClass[RC->getID()];
66
if (Tag !=
RCI
.Tag)
68
return
RCI
;
/external/llvm/lib/CodeGen/
RegisterClassInfo.cpp
81
RCInfo &
RCI
= RegClass[RC->getID()];
86
if (!
RCI
.Order)
87
RCI
.Order.reset(new MCPhysReg[NumRegs]);
112
RCI
.Order[N++] = PhysReg;
116
RCI
.NumRegs = N + CSRAlias.size();
117
assert (
RCI
.NumRegs <= NumRegs && "Allocation order larger than regclass");
125
RCI
.Order[N++] = PhysReg;
130
if (StressRA &&
RCI
.NumRegs > StressRA)
131
RCI
.NumRegs = StressRA;
136
if (Super != RC && getNumAllocatableRegs(Super) >
RCI
.NumRegs
[
all
...]
ShrinkWrap.cpp
101
RegisterClassInfo
RCI
;
161
RCI
.runOnMachineFunction(MF);
238
UseOrDefCSR =
RCI
.getLastCalleeSavedAlias(PhysReg);
RegAllocGreedy.cpp
122
RegisterClassInfo
RCI
;
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
RegisterClassInfo.cpp
93
RCInfo &
RCI
= RegClass[RC->getID()];
98
if (!
RCI
.Order)
99
RCI
.Order.reset(new MCPhysReg[NumRegs]);
124
RCI
.Order[N++] = PhysReg;
128
RCI
.NumRegs = N + CSRAlias.size();
129
assert(
RCI
.NumRegs <= NumRegs && "Allocation order larger than regclass");
137
RCI
.Order[N++] = PhysReg;
142
if (StressRA &&
RCI
.NumRegs > StressRA)
143
RCI
.NumRegs = StressRA;
148
if (Super != RC && getNumAllocatableRegs(Super) >
RCI
.NumRegs
[
all
...]
ShrinkWrap.cpp
112
RegisterClassInfo
RCI
;
189
RCI
.runOnMachineFunction(MF);
284
RCI
.getLastCalleeSavedAlias(PhysReg);
RegAllocGreedy.cpp
165
RegisterClassInfo
RCI
;
[
all
...]
/external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h
71
const RCInfo &
RCI
= RegClass[RC->getID()];
72
if (Tag !=
RCI
.Tag)
74
return
RCI
;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
RegisterClassInfo.h
75
const RCInfo &
RCI
= RegClass[RC->getID()];
76
if (Tag !=
RCI
.Tag)
78
return
RCI
;
/external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp
117
RegisterClassInfo
RCI
;
326
RCI
.runOnMachineFunction(F);
534
auto Ord =
RCI
.getOrder(TRI->getRegClass(RegClassID));
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp
113
RegisterClassInfo
RCI
;
322
RCI
.runOnMachineFunction(F);
521
auto Ord =
RCI
.getOrder(TRI->getRegClass(RegClassID));
Completed in 360 milliseconds