| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| Nios2ISelLowering.cpp | 110 MVT RegVT = VA.getLocVT();
112 const TargetRegisterClass *RC = getRegClassFor(RegVT);
117 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
130 DAG.getNode(Opcode, DL, RegVT, ArgValue, DAG.getValueType(ValVT));
135 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
136 (RegVT == MVT::i64 && ValVT == MVT::f64))
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 238 EVT RegVT = Ins[i].VT;
239 TargetRegisterClass* TRC = getRegClassFor(RegVT);
245 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain,
299 EVT RegVT = Outs[i].VT;
303 if (RegVT == MVT::i1) {
306 else if (RegVT == MVT::i16) {
309 else if (RegVT == MVT::i32) {
312 else if (RegVT == MVT::i64) {
315 else if (RegVT == MVT::f32) {
318 else if (RegVT == MVT::f64)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 174 EVT RegVT = VA.getLocVT();
175 switch (RegVT.getSimpleVT().SimpleTy) {
178 << RegVT.getEVTString() << '\n';
184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 185 EVT RegVT = VA.getLocVT();
189 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
193 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
199 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
202 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
281 EVT RegVT;
|
| LegalizeDAG.cpp | 406 EVT RegVT =
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
523 unsigned RegBytes = RegVT.getSizeInBits() / 8;
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr
[all...] |
| LegalizeIntegerTypes.cpp | 696 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
698 // The argument is passed as NumRegs registers of type RegVT.
702 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
718 DAG.getConstant(i * RegVT.getSizeInBits(),
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 721 MVT RegVT = VA.getLocVT();
729 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
732 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
735 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 326 EVT RegVT = VA.getLocVT();
327 switch (RegVT.getSimpleVT().SimpleTy) {
332 << RegVT.getSimpleVT().SimpleTy << "\n";
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 486 EVT RegVT = VA.getLocVT();
487 switch (RegVT.getSimpleVT().SimpleTy) {
490 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n");
496 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 228 EVT RegVT = VA.getLocVT();
229 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
233 << RegVT.getEVTString() << '\n';
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 291 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
297 MVT RegVT;
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 444 EVT RegVT = VA.getLocVT();
445 switch (RegVT.getSimpleVT().SimpleTy) {
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
469 << RegVT.getEVTString() << "\n");
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 436 EVT RegVT = VA.getLocVT();
437 switch (RegVT.getSimpleVT().SimpleTy) {
442 << RegVT.getEVTString() << "\n";
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 308 MVT RegVT;
321 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 460 EVT RegVT = VA.getLocVT();
461 switch (RegVT.getSimpleVT().SimpleTy) {
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
485 << RegVT.getEVTString() << "\n");
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 618 EVT RegVT = VA.getLocVT();
619 switch (RegVT.getSimpleVT().SimpleTy) {
624 << RegVT.getEVTString() << "\n";
631 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
637 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
640 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
