1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 7 #define __ARCH_FSL_LSCH2_IMMAP_H__ 8 9 #include <fsl_immap.h> 10 11 #define CONFIG_SYS_IMMR 0x01000000 12 #define CONFIG_SYS_DCSRBAR 0x20000000 13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 15 16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 23 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 26 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 27 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 28 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 29 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 30 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 33 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 34 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 35 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 36 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 37 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 38 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 39 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 40 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 41 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 42 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 43 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 44 45 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 46 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 47 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 48 CONFIG_SYS_BMAN_MEM_BASE) 49 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 50 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 51 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 52 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 53 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 54 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 55 CONFIG_SYS_BMAN_CENA_SIZE) 56 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 57 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 58 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 59 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 60 #define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ 61 CONFIG_SYS_QMAN_MEM_BASE) 62 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 63 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 64 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 65 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 66 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 67 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 68 CONFIG_SYS_QMAN_CENA_SIZE) 69 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 70 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 71 72 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 73 74 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 75 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 76 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 77 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 78 79 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 80 81 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 82 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 83 84 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 85 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 86 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 87 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 88 89 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 90 91 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 92 93 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 94 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 95 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 96 /* LUT registers */ 97 #ifdef CONFIG_ARCH_LS1012A 98 #define PCIE_LUT_BASE 0xC0000 99 #else 100 #define PCIE_LUT_BASE 0x10000 101 #endif 102 #define PCIE_LUT_LCTRL0 0x7F8 103 #define PCIE_LUT_DBG 0x7FC 104 105 /* TZ Address Space Controller Definitions */ 106 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 107 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 108 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 109 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 110 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 111 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 112 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 113 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 114 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 115 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 116 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 117 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 118 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 119 120 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 121 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 122 #define TP_ITYP_TYPE_ARM 0x0 123 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 124 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 125 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 126 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 127 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 128 #define TY_ITYP_VER_A7 0x1 129 #define TY_ITYP_VER_A53 0x2 130 #define TY_ITYP_VER_A57 0x3 131 #define TY_ITYP_VER_A72 0x4 132 133 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 134 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 135 #define TP_INIT_PER_CLUSTER 4 136 137 /* 138 * Define default values for some CCSR macros to make header files cleaner* 139 * 140 * To completely disable CCSR relocation in a board header file, define 141 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 142 * to a value that is the same as CONFIG_SYS_CCSRBAR. 143 */ 144 145 #ifdef CONFIG_SYS_CCSRBAR_PHYS 146 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 147 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 148 #endif 149 150 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 151 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 152 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 153 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 154 #endif 155 156 #ifndef CONFIG_SYS_CCSRBAR 157 #define CONFIG_SYS_CCSRBAR 0x01000000 158 #endif 159 160 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 161 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 162 #endif 163 164 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 165 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 166 #endif 167 168 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 169 CONFIG_SYS_CCSRBAR_PHYS_LOW) 170 171 struct sys_info { 172 unsigned long freq_processor[CONFIG_MAX_CPUS]; 173 /* frequency of platform PLL */ 174 unsigned long freq_systembus; 175 unsigned long freq_ddrbus; 176 unsigned long freq_localbus; 177 unsigned long freq_sdhc; 178 #ifdef CONFIG_SYS_DPAA_FMAN 179 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 180 #endif 181 unsigned long freq_qman; 182 }; 183 184 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 185 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 186 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 187 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 188 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 189 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 190 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 191 192 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 193 #define CONFIG_SYS_FSL_FM1_ADDR \ 194 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 195 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 196 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 197 198 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 199 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 200 #define CONFIG_SYS_FSL_SEC_ADDR \ 201 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 202 #define CONFIG_SYS_FSL_JR0_ADDR \ 203 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 204 205 /* Device Configuration and Pin Control */ 206 #define DCFG_DCSR_PORCR1 0x0 207 #define DCFG_DCSR_ECCCR2 0x524 208 #define DISABLE_PFE_ECC BIT(13) 209 210 struct ccsr_gur { 211 u32 porsr1; /* POR status 1 */ 212 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 213 u32 porsr2; /* POR status 2 */ 214 u8 res_008[0x20-0x8]; 215 u32 gpporcr1; /* General-purpose POR configuration */ 216 u32 gpporcr2; 217 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 218 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 219 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 220 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 221 u32 dcfg_fusesr; /* Fuse status register */ 222 u8 res_02c[0x70-0x2c]; 223 u32 devdisr; /* Device disable control */ 224 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 225 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 226 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 227 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 228 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 229 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 230 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 231 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 232 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 233 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 234 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 235 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 236 u32 devdisr2; /* Device disable control 2 */ 237 u32 devdisr3; /* Device disable control 3 */ 238 u32 devdisr4; /* Device disable control 4 */ 239 u32 devdisr5; /* Device disable control 5 */ 240 u32 devdisr6; /* Device disable control 6 */ 241 u32 devdisr7; /* Device disable control 7 */ 242 u8 res_08c[0x94-0x8c]; 243 u32 coredisru; /* uppper portion for support of 64 cores */ 244 u32 coredisrl; /* lower portion for support of 64 cores */ 245 u8 res_09c[0xa0-0x9c]; 246 u32 pvr; /* Processor version */ 247 u32 svr; /* System version */ 248 u32 mvr; /* Manufacturing version */ 249 u8 res_0ac[0xb0-0xac]; 250 u32 rstcr; /* Reset control */ 251 u32 rstrqpblsr; /* Reset request preboot loader status */ 252 u8 res_0b8[0xc0-0xb8]; 253 u32 rstrqmr1; /* Reset request mask */ 254 u8 res_0c4[0xc8-0xc4]; 255 u32 rstrqsr1; /* Reset request status */ 256 u8 res_0cc[0xd4-0xcc]; 257 u32 rstrqwdtmrl; /* Reset request WDT mask */ 258 u8 res_0d8[0xdc-0xd8]; 259 u32 rstrqwdtsrl; /* Reset request WDT status */ 260 u8 res_0e0[0xe4-0xe0]; 261 u32 brrl; /* Boot release */ 262 u8 res_0e8[0x100-0xe8]; 263 u32 rcwsr[16]; /* Reset control word status */ 264 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 265 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 266 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 267 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 268 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 269 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 270 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 271 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 272 #define RCW_SB_EN_REG_INDEX 7 273 #define RCW_SB_EN_MASK 0x00200000 274 275 u8 res_140[0x200-0x140]; 276 u32 scratchrw[4]; /* Scratch Read/Write */ 277 u8 res_210[0x300-0x210]; 278 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 279 u8 res_310[0x400-0x310]; 280 u32 crstsr[12]; 281 u8 res_430[0x500-0x430]; 282 283 /* PCI Express n Logical I/O Device Number register */ 284 u32 dcfg_ccsr_pex1liodnr; 285 u32 dcfg_ccsr_pex2liodnr; 286 u32 dcfg_ccsr_pex3liodnr; 287 u32 dcfg_ccsr_pex4liodnr; 288 /* RIO n Logical I/O Device Number register */ 289 u32 dcfg_ccsr_rio1liodnr; 290 u32 dcfg_ccsr_rio2liodnr; 291 u32 dcfg_ccsr_rio3liodnr; 292 u32 dcfg_ccsr_rio4liodnr; 293 /* USB Logical I/O Device Number register */ 294 u32 dcfg_ccsr_usb1liodnr; 295 u32 dcfg_ccsr_usb2liodnr; 296 u32 dcfg_ccsr_usb3liodnr; 297 u32 dcfg_ccsr_usb4liodnr; 298 /* SD/MMC Logical I/O Device Number register */ 299 u32 dcfg_ccsr_sdmmc1liodnr; 300 u32 dcfg_ccsr_sdmmc2liodnr; 301 u32 dcfg_ccsr_sdmmc3liodnr; 302 u32 dcfg_ccsr_sdmmc4liodnr; 303 /* RIO Message Unit Logical I/O Device Number register */ 304 u32 dcfg_ccsr_riomaintliodnr; 305 306 u8 res_544[0x550-0x544]; 307 u32 sataliodnr[4]; 308 u8 res_560[0x570-0x560]; 309 310 u32 dcfg_ccsr_misc1liodnr; 311 u32 dcfg_ccsr_misc2liodnr; 312 u32 dcfg_ccsr_misc3liodnr; 313 u32 dcfg_ccsr_misc4liodnr; 314 u32 dcfg_ccsr_dma1liodnr; 315 u32 dcfg_ccsr_dma2liodnr; 316 u32 dcfg_ccsr_dma3liodnr; 317 u32 dcfg_ccsr_dma4liodnr; 318 u32 dcfg_ccsr_spare1liodnr; 319 u32 dcfg_ccsr_spare2liodnr; 320 u32 dcfg_ccsr_spare3liodnr; 321 u32 dcfg_ccsr_spare4liodnr; 322 u8 res_5a0[0x600-0x5a0]; 323 u32 dcfg_ccsr_pblsr; 324 325 u32 pamubypenr; 326 u32 dmacr1; 327 328 u8 res_60c[0x610-0x60c]; 329 u32 dcfg_ccsr_gensr1; 330 u32 dcfg_ccsr_gensr2; 331 u32 dcfg_ccsr_gensr3; 332 u32 dcfg_ccsr_gensr4; 333 u32 dcfg_ccsr_gencr1; 334 u32 dcfg_ccsr_gencr2; 335 u32 dcfg_ccsr_gencr3; 336 u32 dcfg_ccsr_gencr4; 337 u32 dcfg_ccsr_gencr5; 338 u32 dcfg_ccsr_gencr6; 339 u32 dcfg_ccsr_gencr7; 340 u8 res_63c[0x658-0x63c]; 341 u32 dcfg_ccsr_cgensr1; 342 u32 dcfg_ccsr_cgensr0; 343 u8 res_660[0x678-0x660]; 344 u32 dcfg_ccsr_cgencr1; 345 346 u32 dcfg_ccsr_cgencr0; 347 u8 res_680[0x700-0x680]; 348 u32 dcfg_ccsr_sriopstecr; 349 u32 dcfg_ccsr_dcsrcr; 350 351 u8 res_708[0x740-0x708]; /* add more registers when needed */ 352 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 353 struct { 354 u32 upper; 355 u32 lower; 356 } tp_cluster[16]; 357 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 358 u32 dcfg_ccsr_qmbm_warmrst; 359 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 360 u32 dcfg_ccsr_reserved0; 361 u32 dcfg_ccsr_reserved1; 362 }; 363 364 #define SCFG_QSPI_CLKSEL 0x40100000 365 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 366 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 367 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 368 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 369 #define SCFG_USBPWRFAULT_SHARED 0x00000001 370 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 371 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 372 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 373 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 374 375 #define SCFG_BASE 0x01570000 376 #define SCFG_USB3PRM1CR_USB1 0x070 377 #define SCFG_USB3PRM2CR_USB1 0x074 378 #define SCFG_USB3PRM1CR_USB2 0x07C 379 #define SCFG_USB3PRM2CR_USB2 0x080 380 #define SCFG_USB3PRM1CR_USB3 0x088 381 #define SCFG_USB3PRM2CR_USB3 0x08c 382 #define SCFG_USB_TXVREFTUNE 0x9 383 #define SCFG_USB_SQRXTUNE_MASK 0x7 384 #define SCFG_USB_PCSTXSWINGFULL 0x47 385 #define SCFG_USB_PHY1 0x084F0000 386 #define SCFG_USB_PHY2 0x08500000 387 #define SCFG_USB_PHY3 0x08510000 388 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 389 #define USB_PHY_RX_EQ_VAL_1 0x0000 390 #define USB_PHY_RX_EQ_VAL_2 0x0080 391 #define USB_PHY_RX_EQ_VAL_3 0x0380 392 #define USB_PHY_RX_EQ_VAL_4 0x0b80 393 394 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 395 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 396 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 397 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 398 399 /* RGMIIPCR bit definitions*/ 400 #define SCFG_RGMIIPCR_EN_AUTO BIT(3) 401 #define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 402 #define SCFG_RGMIIPCR_SETSP_100M 0 403 #define SCFG_RGMIIPCR_SETSP_10M BIT(1) 404 #define SCFG_RGMIIPCR_SETFD BIT(0) 405 406 /* PFEASBCR bit definitions */ 407 #define SCFG_PFEASBCR_ARCACHE0 BIT(31) 408 #define SCFG_PFEASBCR_AWCACHE0 BIT(30) 409 #define SCFG_PFEASBCR_ARCACHE1 BIT(29) 410 #define SCFG_PFEASBCR_AWCACHE1 BIT(28) 411 #define SCFG_PFEASBCR_ARSNP BIT(27) 412 #define SCFG_PFEASBCR_AWSNP BIT(26) 413 414 /* WR_QoS1 PFE bit definitions */ 415 #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 416 #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 417 418 /* RD_QoS1 PFE bit definitions */ 419 #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 420 #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 421 422 /* Supplemental Configuration Unit */ 423 struct ccsr_scfg { 424 u8 res_000[0x100-0x000]; 425 u32 usb2_icid; 426 u32 usb3_icid; 427 u8 res_108[0x114-0x108]; 428 u32 dma_icid; 429 u32 sata_icid; 430 u32 usb1_icid; 431 u32 qe_icid; 432 u32 sdhc_icid; 433 u32 edma_icid; 434 u32 etr_icid; 435 u32 core_sft_rst[4]; 436 u8 res_140[0x158-0x140]; 437 u32 altcbar; 438 u32 qspi_cfg; 439 u8 res_160[0x164 - 0x160]; 440 u32 wr_qos1; 441 u32 wr_qos2; 442 u32 rd_qos1; 443 u32 rd_qos2; 444 u8 res_174[0x180 - 0x174]; 445 u32 dmamcr; 446 u8 res_184[0x188-0x184]; 447 u32 gic_align; 448 u32 debug_icid; 449 u8 res_190[0x1a4-0x190]; 450 u32 snpcnfgcr; 451 u8 res_1a8[0x1ac-0x1a8]; 452 u32 intpcr; 453 u8 res_1b0[0x204-0x1b0]; 454 u32 coresrencr; 455 u8 res_208[0x220-0x208]; 456 u32 rvbar0_0; 457 u32 rvbar0_1; 458 u32 rvbar1_0; 459 u32 rvbar1_1; 460 u32 rvbar2_0; 461 u32 rvbar2_1; 462 u32 rvbar3_0; 463 u32 rvbar3_1; 464 u32 lpmcsr; 465 u8 res_244[0x400-0x244]; 466 u32 qspidqscr; 467 u32 ecgtxcmcr; 468 u32 sdhciovselcr; 469 u32 rcwpmuxcr0; 470 u32 usbdrvvbus_selcr; 471 u32 usbpwrfault_selcr; 472 u32 usb_refclk_selcr1; 473 u32 usb_refclk_selcr2; 474 u32 usb_refclk_selcr3; 475 u8 res_424[0x434 - 0x424]; 476 u32 rgmiipcr; 477 u32 res_438; 478 u32 rgmiipsr; 479 u32 pfepfcssr1; 480 u32 pfeintencr1; 481 u32 pfepfcssr2; 482 u32 pfeintencr2; 483 u32 pfeerrcr; 484 u32 pfeeerrintencr; 485 u32 pfeasbcr; 486 u32 pfebsbcr; 487 u8 res_460[0x484 - 0x460]; 488 u32 mdioselcr; 489 u8 res_468[0x600 - 0x488]; 490 u32 scratchrw[4]; 491 u8 res_610[0x680-0x610]; 492 u32 corebcr; 493 u8 res_684[0x1000-0x684]; 494 u32 pex1msiir; 495 u32 pex1msir; 496 u8 res_1008[0x2000-0x1008]; 497 u32 pex2; 498 u32 pex2msir; 499 u8 res_2008[0x3000-0x2008]; 500 u32 pex3msiir; 501 u32 pex3msir; 502 }; 503 504 /* Clocking */ 505 struct ccsr_clk { 506 struct { 507 u32 clkcncsr; /* core cluster n clock control status */ 508 u8 res_004[0x0c]; 509 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 510 u8 res_014[0x0c]; 511 } clkcsr[4]; 512 u8 res_040[0x780]; /* 0x100 */ 513 struct { 514 u32 pllcngsr; 515 u8 res_804[0x1c]; 516 } pllcgsr[2]; 517 u8 res_840[0x1c0]; 518 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 519 u8 res_a04[0x1fc]; 520 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 521 u8 res_c04[0x1c]; 522 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 523 u8 res_c24[0x3dc]; 524 }; 525 526 /* System Counter */ 527 struct sctr_regs { 528 u32 cntcr; 529 u32 cntsr; 530 u32 cntcv1; 531 u32 cntcv2; 532 u32 resv1[4]; 533 u32 cntfid0; 534 u32 cntfid1; 535 u32 resv2[1002]; 536 u32 counterid[12]; 537 }; 538 539 #define SRDS_MAX_LANES 4 540 struct ccsr_serdes { 541 struct { 542 u32 rstctl; /* Reset Control Register */ 543 #define SRDS_RSTCTL_RST 0x80000000 544 #define SRDS_RSTCTL_RSTDONE 0x40000000 545 #define SRDS_RSTCTL_RSTERR 0x20000000 546 #define SRDS_RSTCTL_SWRST 0x10000000 547 #define SRDS_RSTCTL_SDEN 0x00000020 548 #define SRDS_RSTCTL_SDRST_B 0x00000040 549 #define SRDS_RSTCTL_PLLRST_B 0x00000080 550 u32 pllcr0; /* PLL Control Register 0 */ 551 #define SRDS_PLLCR0_POFF 0x80000000 552 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 553 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 554 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 555 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 556 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 557 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 558 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 559 #define SRDS_PLLCR0_PLL_LCK 0x00800000 560 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 561 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 562 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 563 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 564 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 565 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 566 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 567 u32 pllcr1; /* PLL Control Register 1 */ 568 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 569 u32 res_0c; /* 0x00c */ 570 u32 pllcr3; 571 u32 pllcr4; 572 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 573 u8 res_1c[0x20-0x1c]; 574 } bank[2]; 575 u8 res_40[0x90-0x40]; 576 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 577 u8 res_94[0xa0-0x94]; 578 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 579 u8 res_a4[0xb0-0xa4]; 580 u32 srdsgr0; /* 0xb0 General Register 0 */ 581 u8 res_b4[0x100-0xb4]; 582 struct { 583 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 584 u8 res_104[0x120-0x104]; 585 } lnpssr[4]; /* Lane A, B, C, D */ 586 u8 res_180[0x200-0x180]; 587 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 588 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 589 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 590 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 591 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 592 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 593 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 594 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 595 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 596 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 597 u32 srdspccra; /* 0x228 Protocol Configuration A */ 598 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 599 u8 res_230[0x800-0x230]; 600 struct { 601 u32 gcr0; /* 0x800 General Control Register 0 */ 602 u32 gcr1; /* 0x804 General Control Register 1 */ 603 u32 gcr2; /* 0x808 General Control Register 2 */ 604 u32 sscr0; 605 u32 recr0; /* 0x810 Receive Equalization Control */ 606 u32 recr1; 607 u32 tecr0; /* 0x818 Transmit Equalization Control */ 608 u32 sscr1; 609 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 610 u8 res_824[0x83c-0x824]; 611 u32 tcsr3; 612 } lane[4]; /* Lane A, B, C, D */ 613 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 614 struct { 615 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 616 u8 res_1004[0x1040-0x1004]; 617 } pcie[3]; 618 u8 res_10c0[0x1800-0x10c0]; 619 struct { 620 u8 res_1800[0x1804-0x1800]; 621 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 622 u8 res_1808[0x180c-0x1808]; 623 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 624 } sgmii[4]; /* Lane A, B, C, D */ 625 u8 res_1840[0x1880-0x1840]; 626 struct { 627 u8 res_1880[0x1884-0x1880]; 628 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 629 u8 res_1888[0x188c-0x1888]; 630 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 631 } qsgmii[2]; /* Lane A, B */ 632 u8 res_18a0[0x1980-0x18a0]; 633 struct { 634 u8 res_1980[0x1984-0x1980]; 635 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 636 u8 res_1988[0x198c-0x1988]; 637 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 638 } xfi[2]; /* Lane A, B */ 639 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 640 }; 641 642 struct ccsr_gpio { 643 u32 gpdir; 644 u32 gpodr; 645 u32 gpdat; 646 u32 gpier; 647 u32 gpimr; 648 u32 gpicr; 649 u32 gpibe; 650 }; 651 652 /* MMU 500 */ 653 #define SMMU_SCR0 (SMMU_BASE + 0x0) 654 #define SMMU_SCR1 (SMMU_BASE + 0x4) 655 #define SMMU_SCR2 (SMMU_BASE + 0x8) 656 #define SMMU_SACR (SMMU_BASE + 0x10) 657 #define SMMU_IDR0 (SMMU_BASE + 0x20) 658 #define SMMU_IDR1 (SMMU_BASE + 0x24) 659 660 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 661 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 662 #define SMMU_NSACR (SMMU_BASE + 0x410) 663 664 #define SCR0_CLIENTPD_MASK 0x00000001 665 #define SCR0_USFCFG_MASK 0x00000400 666 667 uint get_svr(void); 668 669 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 670
