1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keithw (at) vmware.com> 30 */ 31 32 33 #ifndef BRW_STATE_H 34 #define BRW_STATE_H 35 36 #include "brw_context.h" 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 enum intel_msaa_layout; 43 44 extern const struct brw_tracked_state brw_blend_constant_color; 45 extern const struct brw_tracked_state brw_clip_unit; 46 extern const struct brw_tracked_state brw_vs_pull_constants; 47 extern const struct brw_tracked_state brw_tcs_pull_constants; 48 extern const struct brw_tracked_state brw_tes_pull_constants; 49 extern const struct brw_tracked_state brw_gs_pull_constants; 50 extern const struct brw_tracked_state brw_wm_pull_constants; 51 extern const struct brw_tracked_state brw_cs_pull_constants; 52 extern const struct brw_tracked_state brw_constant_buffer; 53 extern const struct brw_tracked_state brw_curbe_offsets; 54 extern const struct brw_tracked_state brw_binding_table_pointers; 55 extern const struct brw_tracked_state brw_depthbuffer; 56 extern const struct brw_tracked_state brw_recalculate_urb_fence; 57 extern const struct brw_tracked_state brw_sf_vp; 58 extern const struct brw_tracked_state brw_cs_texture_surfaces; 59 extern const struct brw_tracked_state brw_vs_ubo_surfaces; 60 extern const struct brw_tracked_state brw_vs_image_surfaces; 61 extern const struct brw_tracked_state brw_tcs_ubo_surfaces; 62 extern const struct brw_tracked_state brw_tcs_image_surfaces; 63 extern const struct brw_tracked_state brw_tes_ubo_surfaces; 64 extern const struct brw_tracked_state brw_tes_image_surfaces; 65 extern const struct brw_tracked_state brw_gs_ubo_surfaces; 66 extern const struct brw_tracked_state brw_gs_image_surfaces; 67 extern const struct brw_tracked_state brw_renderbuffer_surfaces; 68 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces; 69 extern const struct brw_tracked_state brw_texture_surfaces; 70 extern const struct brw_tracked_state brw_wm_binding_table; 71 extern const struct brw_tracked_state brw_gs_binding_table; 72 extern const struct brw_tracked_state brw_tes_binding_table; 73 extern const struct brw_tracked_state brw_tcs_binding_table; 74 extern const struct brw_tracked_state brw_vs_binding_table; 75 extern const struct brw_tracked_state brw_wm_ubo_surfaces; 76 extern const struct brw_tracked_state brw_wm_image_surfaces; 77 extern const struct brw_tracked_state brw_cs_ubo_surfaces; 78 extern const struct brw_tracked_state brw_cs_image_surfaces; 79 80 extern const struct brw_tracked_state brw_psp_urb_cbs; 81 82 extern const struct brw_tracked_state brw_indices; 83 extern const struct brw_tracked_state brw_index_buffer; 84 extern const struct brw_tracked_state gen7_cs_push_constants; 85 extern const struct brw_tracked_state gen6_binding_table_pointers; 86 extern const struct brw_tracked_state gen6_gs_binding_table; 87 extern const struct brw_tracked_state gen6_renderbuffer_surfaces; 88 extern const struct brw_tracked_state gen6_sampler_state; 89 extern const struct brw_tracked_state gen6_sol_surface; 90 extern const struct brw_tracked_state gen6_sf_vp; 91 extern const struct brw_tracked_state gen6_urb; 92 extern const struct brw_tracked_state gen7_depthbuffer; 93 extern const struct brw_tracked_state gen7_l3_state; 94 extern const struct brw_tracked_state gen7_push_constant_space; 95 extern const struct brw_tracked_state gen7_urb; 96 extern const struct brw_tracked_state gen8_pma_fix; 97 extern const struct brw_tracked_state brw_cs_work_groups_surface; 98 99 static inline bool 100 brw_state_dirty(const struct brw_context *brw, 101 GLuint mesa_flags, uint64_t brw_flags) 102 { 103 return ((brw->NewGLState & mesa_flags) | 104 (brw->ctx.NewDriverState & brw_flags)) != 0; 105 } 106 107 /* brw_binding_tables.c */ 108 void brw_upload_binding_table(struct brw_context *brw, 109 uint32_t packet_name, 110 const struct brw_stage_prog_data *prog_data, 111 struct brw_stage_state *stage_state); 112 113 /* brw_misc_state.c */ 114 void brw_upload_invariant_state(struct brw_context *brw); 115 uint32_t 116 brw_depthbuffer_format(struct brw_context *brw); 117 118 uint32_t 119 brw_convert_depth_value(mesa_format format, float value); 120 121 void brw_upload_state_base_address(struct brw_context *brw); 122 123 /* gen8_depth_state.c */ 124 void gen8_write_pma_stall_bits(struct brw_context *brw, 125 uint32_t pma_stall_bits); 126 127 /* brw_disk_cache.c */ 128 void brw_disk_cache_init(struct brw_context *brw); 129 bool brw_disk_cache_upload_program(struct brw_context *brw, 130 gl_shader_stage stage); 131 void brw_disk_cache_write_compute_program(struct brw_context *brw); 132 void brw_disk_cache_write_render_programs(struct brw_context *brw); 133 134 /*********************************************************************** 135 * brw_state.c 136 */ 137 void brw_upload_render_state(struct brw_context *brw); 138 void brw_render_state_finished(struct brw_context *brw); 139 void brw_upload_compute_state(struct brw_context *brw); 140 void brw_compute_state_finished(struct brw_context *brw); 141 void brw_init_state(struct brw_context *brw); 142 void brw_destroy_state(struct brw_context *brw); 143 void brw_emit_select_pipeline(struct brw_context *brw, 144 enum brw_pipeline pipeline); 145 146 static inline void 147 brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) 148 { 149 if (unlikely(brw->last_pipeline != pipeline)) { 150 assert(pipeline < BRW_NUM_PIPELINES); 151 brw_emit_select_pipeline(brw, pipeline); 152 brw->last_pipeline = pipeline; 153 } 154 } 155 156 /*********************************************************************** 157 * brw_program_cache.c 158 */ 159 160 void brw_upload_cache(struct brw_cache *cache, 161 enum brw_cache_id cache_id, 162 const void *key, 163 GLuint key_sz, 164 const void *data, 165 GLuint data_sz, 166 const void *aux, 167 GLuint aux_sz, 168 uint32_t *out_offset, void *out_aux); 169 170 bool brw_search_cache(struct brw_cache *cache, 171 enum brw_cache_id cache_id, 172 const void *key, 173 GLuint key_size, 174 uint32_t *inout_offset, void *inout_aux); 175 176 const void *brw_find_previous_compile(struct brw_cache *cache, 177 enum brw_cache_id cache_id, 178 unsigned program_string_id); 179 180 void brw_program_cache_check_size(struct brw_context *brw); 181 182 void brw_init_caches( struct brw_context *brw ); 183 void brw_destroy_caches( struct brw_context *brw ); 184 185 void brw_print_program_cache(struct brw_context *brw); 186 187 /* intel_batchbuffer.c */ 188 void brw_require_statebuffer_space(struct brw_context *brw, int size); 189 void *brw_state_batch(struct brw_context *brw, 190 int size, int alignment, uint32_t *out_offset); 191 uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset); 192 193 /* brw_wm_surface_state.c */ 194 uint32_t brw_get_surface_tiling_bits(uint32_t tiling); 195 uint32_t brw_get_surface_num_multisamples(unsigned num_samples); 196 enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format); 197 198 GLuint translate_tex_target(GLenum target); 199 200 enum isl_format translate_tex_format(struct brw_context *brw, 201 mesa_format mesa_format, 202 GLenum srgb_decode); 203 204 int brw_get_texture_swizzle(const struct gl_context *ctx, 205 const struct gl_texture_object *t); 206 207 void brw_emit_buffer_surface_state(struct brw_context *brw, 208 uint32_t *out_offset, 209 struct brw_bo *bo, 210 unsigned buffer_offset, 211 unsigned surface_format, 212 unsigned buffer_size, 213 unsigned pitch, 214 unsigned reloc_flags); 215 216 /* brw_sampler_state.c */ 217 void brw_emit_sampler_state(struct brw_context *brw, 218 uint32_t *sampler_state, 219 uint32_t batch_offset_for_sampler_state, 220 unsigned min_filter, 221 unsigned mag_filter, 222 unsigned mip_filter, 223 unsigned max_anisotropy, 224 unsigned address_rounding, 225 unsigned wrap_s, 226 unsigned wrap_t, 227 unsigned wrap_r, 228 unsigned base_level, 229 unsigned min_lod, 230 unsigned max_lod, 231 int lod_bias, 232 unsigned shadow_function, 233 bool non_normalized_coordinates, 234 uint32_t border_color_offset); 235 236 /* gen6_constant_state.c */ 237 void 238 brw_populate_constant_data(struct brw_context *brw, 239 const struct gl_program *prog, 240 const struct brw_stage_state *stage_state, 241 void *dst, 242 const uint32_t *param, 243 unsigned nr_params); 244 void 245 brw_upload_pull_constants(struct brw_context *brw, 246 GLbitfield64 brw_new_constbuf, 247 const struct gl_program *prog, 248 struct brw_stage_state *stage_state, 249 const struct brw_stage_prog_data *prog_data); 250 void 251 brw_upload_cs_push_constants(struct brw_context *brw, 252 const struct gl_program *prog, 253 const struct brw_cs_prog_data *cs_prog_data, 254 struct brw_stage_state *stage_state); 255 256 /* gen7_vs_state.c */ 257 void 258 gen7_upload_constant_state(struct brw_context *brw, 259 const struct brw_stage_state *stage_state, 260 bool active, unsigned opcode); 261 262 /* brw_clip.c */ 263 void brw_upload_clip_prog(struct brw_context *brw); 264 265 /* brw_sf.c */ 266 void brw_upload_sf_prog(struct brw_context *brw); 267 268 bool brw_is_drawing_points(const struct brw_context *brw); 269 bool brw_is_drawing_lines(const struct brw_context *brw); 270 271 /* gen7_l3_state.c */ 272 void 273 gen7_restore_default_l3_config(struct brw_context *brw); 274 275 static inline bool 276 use_state_point_size(const struct brw_context *brw) 277 { 278 const struct gl_context *ctx = &brw->ctx; 279 280 /* Section 14.4 (Points) of the OpenGL 4.5 specification says: 281 * 282 * "If program point size mode is enabled, the derived point size is 283 * taken from the (potentially clipped) shader built-in gl_PointSize 284 * written by: 285 * 286 * * the geometry shader, if active; 287 * * the tessellation evaluation shader, if active and no 288 * geometry shader is active; 289 * * the vertex shader, otherwise 290 * 291 * and clamped to the implementation-dependent point size range. If 292 * the value written to gl_PointSize is less than or equal to zero, 293 * or if no value was written to gl_PointSize, results are undefined. 294 * If program point size mode is disabled, the derived point size is 295 * specified with the command 296 * 297 * void PointSize(float size); 298 * 299 * size specifies the requested size of a point. The default value 300 * is 1.0." 301 * 302 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and 303 * OES_tessellation_point_size specifications. To summarize: if the last 304 * stage before rasterization is a GS or TES, then use gl_PointSize from 305 * the shader if written. Otherwise, use 1.0. If the last stage is a 306 * vertex shader, use gl_PointSize, or it is undefined. 307 * 308 * We can combine these rules into a single condition for both APIs. 309 * Using the state point size when the last shader stage doesn't write 310 * gl_PointSize satisfies GL's requirements, as it's undefined. Because 311 * ES doesn't have a PointSize() command, the state point size will 312 * remain 1.0, satisfying the ES default value in the GS/TES case, and 313 * the VS case (1.0 works for "undefined"). Mesa sets the program point 314 * mode flag to always-enabled in ES, so we can safely check that, and 315 * it'll be ignored for ES. 316 * 317 * _NEW_PROGRAM | _NEW_POINT 318 * BRW_NEW_VUE_MAP_GEOM_OUT 319 */ 320 return (!ctx->VertexProgram.PointSizeEnabled && !ctx->Point._Attenuated) || 321 (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0; 322 } 323 324 void brw_copy_pipeline_atoms(struct brw_context *brw, 325 enum brw_pipeline pipeline, 326 const struct brw_tracked_state **atoms, 327 int num_atoms); 328 void gen4_init_atoms(struct brw_context *brw); 329 void gen45_init_atoms(struct brw_context *brw); 330 void gen5_init_atoms(struct brw_context *brw); 331 void gen6_init_atoms(struct brw_context *brw); 332 void gen7_init_atoms(struct brw_context *brw); 333 void gen75_init_atoms(struct brw_context *brw); 334 void gen8_init_atoms(struct brw_context *brw); 335 void gen9_init_atoms(struct brw_context *brw); 336 void gen10_init_atoms(struct brw_context *brw); 337 338 /* Memory Object Control State: 339 * Specifying zero for L3 means "uncached in L3", at least on Haswell 340 * and Baytrail, since there are no PTE flags for setting L3 cacheability. 341 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0 342 * may still respect that. 343 */ 344 #define GEN7_MOCS_L3 1 345 346 /* Ivybridge only: cache in LLC. 347 * Specifying zero here means to use the PTE values set by the kernel; 348 * non-zero overrides the PTE values. 349 */ 350 #define IVB_MOCS_LLC (1 << 1) 351 352 /* Baytrail only: snoop in CPU cache */ 353 #define BYT_MOCS_SNOOP (1 << 1) 354 355 /* Haswell only: LLC/eLLC controls (write-back or uncached). 356 * Specifying zero here means to use the PTE values set by the kernel, 357 * which is useful since it offers additional control (write-through 358 * cacheing and age). Non-zero overrides the PTE values. 359 */ 360 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1) 361 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1) 362 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1) 363 364 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC), 365 * and let you force write-back (WB) or write-through (WT) caching, or leave 366 * it up to the page table entry (PTE) specified by the kernel. 367 */ 368 #define BDW_MOCS_WB 0x78 369 #define BDW_MOCS_WT 0x58 370 #define BDW_MOCS_PTE 0x18 371 372 /* Skylake: MOCS is now an index into an array of 62 different caching 373 * configurations programmed by the kernel. 374 */ 375 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ 376 #define SKL_MOCS_WB (2 << 1) 377 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */ 378 #define SKL_MOCS_PTE (1 << 1) 379 380 /* Cannonlake: MOCS is now an index into an array of 62 different caching 381 * configurations programmed by the kernel. 382 */ 383 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ 384 #define CNL_MOCS_WB (2 << 1) 385 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */ 386 #define CNL_MOCS_PTE (1 << 1) 387 388 uint32_t brw_get_bo_mocs(const struct gen_device_info *devinfo, 389 struct brw_bo *bo); 390 391 #ifdef __cplusplus 392 } 393 #endif 394 395 #endif 396
