1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 * 5 * (C) Copyright 2003 Motorola Inc. 6 * Modified by Xianghua Xiao, X.Xiao (at) motorola.com 7 * 8 * (C) Copyright 2000 9 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 10 */ 11 12 #include <common.h> 13 #include <watchdog.h> 14 #include <asm/processor.h> 15 #include <ioports.h> 16 #include <sata.h> 17 #include <fm_eth.h> 18 #include <asm/io.h> 19 #include <asm/cache.h> 20 #include <asm/mmu.h> 21 #include <fsl_errata.h> 22 #include <asm/fsl_law.h> 23 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_srio.h> 25 #ifdef CONFIG_FSL_CORENET 26 #include <asm/fsl_portals.h> 27 #include <asm/fsl_liodn.h> 28 #include <fsl_qbman.h> 29 #endif 30 #include <fsl_usb.h> 31 #include <hwconfig.h> 32 #include <linux/compiler.h> 33 #include "mp.h" 34 #ifdef CONFIG_CHAIN_OF_TRUST 35 #include <fsl_validate.h> 36 #endif 37 #ifdef CONFIG_FSL_CAAM 38 #include <fsl_sec.h> 39 #endif 40 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) 41 #include <asm/fsl_pamu.h> 42 #include <fsl_secboot_err.h> 43 #endif 44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 45 #include <nand.h> 46 #include <errno.h> 47 #endif 48 #ifndef CONFIG_ARCH_QEMU_E500 49 #include <fsl_ddr.h> 50 #endif 51 #include "../../../../drivers/ata/fsl_sata.h" 52 #ifdef CONFIG_U_QE 53 #include <fsl_qe.h> 54 #endif 55 56 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 57 /* 58 * For deriving usb clock from 100MHz sysclk, reference divisor is set 59 * to a value of 5, which gives an intermediate value 20(100/5). The 60 * multiplication factor integer is set to 24, which when multiplied to 61 * above intermediate value provides clock for usb ip. 62 */ 63 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) 64 { 65 sys_info_t sysinfo; 66 67 get_sys_info(&sysinfo); 68 if (sysinfo.diff_sysclk == 1) { 69 clrbits_be32(&usb_phy->pllprg[1], 70 CONFIG_SYS_FSL_USB_PLLPRG2_MFI); 71 setbits_be32(&usb_phy->pllprg[1], 72 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | 73 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | 74 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); 75 } 76 } 77 #endif 78 79 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 80 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) 81 { 82 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 83 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); 84 85 /* Increase Disconnect Threshold by 50mV */ 86 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 87 INC_DCNT_THRESHOLD_50MV; 88 /* Enable programming of USB High speed Disconnect threshold */ 89 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 90 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); 91 92 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); 93 /* Increase Disconnect Threshold by 50mV */ 94 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | 95 INC_DCNT_THRESHOLD_50MV; 96 /* Enable programming of USB High speed Disconnect threshold */ 97 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; 98 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); 99 #else 100 101 u32 temp = 0; 102 u32 status = in_be32(&usb_phy->status1); 103 104 u32 squelch_prog_rd_0_2 = 105 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) 106 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 107 108 u32 squelch_prog_rd_3_5 = 109 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) 110 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; 111 112 setbits_be32(&usb_phy->config1, 113 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); 114 setbits_be32(&usb_phy->config2, 115 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); 116 117 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; 118 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 119 120 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; 121 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); 122 #endif 123 } 124 #endif 125 126 127 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 128 extern qe_iop_conf_t qe_iop_conf_tab[]; 129 extern void qe_config_iopin(u8 port, u8 pin, int dir, 130 int open_drain, int assign); 131 extern void qe_init(uint qe_base); 132 extern void qe_reset(void); 133 134 static void config_qe_ioports(void) 135 { 136 u8 port, pin; 137 int dir, open_drain, assign; 138 int i; 139 140 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 141 port = qe_iop_conf_tab[i].port; 142 pin = qe_iop_conf_tab[i].pin; 143 dir = qe_iop_conf_tab[i].dir; 144 open_drain = qe_iop_conf_tab[i].open_drain; 145 assign = qe_iop_conf_tab[i].assign; 146 qe_config_iopin(port, pin, dir, open_drain, assign); 147 } 148 } 149 #endif 150 151 #ifdef CONFIG_CPM2 152 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 153 { 154 int portnum; 155 156 for (portnum = 0; portnum < 4; portnum++) { 157 uint pmsk = 0, 158 ppar = 0, 159 psor = 0, 160 pdir = 0, 161 podr = 0, 162 pdat = 0; 163 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 164 iop_conf_t *eiopc = iopc + 32; 165 uint msk = 1; 166 167 /* 168 * NOTE: 169 * index 0 refers to pin 31, 170 * index 31 refers to pin 0 171 */ 172 while (iopc < eiopc) { 173 if (iopc->conf) { 174 pmsk |= msk; 175 if (iopc->ppar) 176 ppar |= msk; 177 if (iopc->psor) 178 psor |= msk; 179 if (iopc->pdir) 180 pdir |= msk; 181 if (iopc->podr) 182 podr |= msk; 183 if (iopc->pdat) 184 pdat |= msk; 185 } 186 187 msk <<= 1; 188 iopc++; 189 } 190 191 if (pmsk != 0) { 192 volatile ioport_t *iop = ioport_addr (cpm, portnum); 193 uint tpmsk = ~pmsk; 194 195 /* 196 * the (somewhat confused) paragraph at the 197 * bottom of page 35-5 warns that there might 198 * be "unknown behaviour" when programming 199 * PSORx and PDIRx, if PPARx = 1, so I 200 * decided this meant I had to disable the 201 * dedicated function first, and enable it 202 * last. 203 */ 204 iop->ppar &= tpmsk; 205 iop->psor = (iop->psor & tpmsk) | psor; 206 iop->podr = (iop->podr & tpmsk) | podr; 207 iop->pdat = (iop->pdat & tpmsk) | pdat; 208 iop->pdir = (iop->pdir & tpmsk) | pdir; 209 iop->ppar |= ppar; 210 } 211 } 212 } 213 #endif 214 215 #ifdef CONFIG_SYS_FSL_CPC 216 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) 217 void disable_cpc_sram(void) 218 { 219 int i; 220 221 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 222 223 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 224 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 225 /* find and disable LAW of SRAM */ 226 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 227 228 if (law.index == -1) { 229 printf("\nFatal error happened\n"); 230 return; 231 } 232 disable_law(law.index); 233 234 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 235 out_be32(&cpc->cpccsr0, 0); 236 out_be32(&cpc->cpcsrcr0, 0); 237 } 238 } 239 } 240 #endif 241 242 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 243 #ifdef CONFIG_POST 244 #error POST memory test cannot be enabled with TDM 245 #endif 246 static void enable_tdm_law(void) 247 { 248 int ret; 249 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; 250 int tdm_hwconfig_enabled = 0; 251 252 /* 253 * Extract hwconfig from environment since environment 254 * is not setup properly yet. Search for tdm entry in 255 * hwconfig. 256 */ 257 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 258 if (ret > 0) { 259 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); 260 /* If tdm is defined in hwconfig, set law for tdm workaround */ 261 if (tdm_hwconfig_enabled) 262 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, 263 LAW_TRGT_IF_CCSR); 264 } 265 } 266 #endif 267 268 void enable_cpc(void) 269 { 270 int i; 271 int ret; 272 u32 size = 0; 273 u32 cpccfg0; 274 char buffer[HWCONFIG_BUFFER_SIZE]; 275 char cpc_subarg[16]; 276 bool have_hwconfig = false; 277 int cpc_args = 0; 278 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 279 280 /* Extract hwconfig from environment */ 281 ret = env_get_f("hwconfig", buffer, sizeof(buffer)); 282 if (ret > 0) { 283 /* 284 * If "en_cpc" is not defined in hwconfig then by default all 285 * cpcs are enable. If this config is defined then individual 286 * cpcs which have to be enabled should also be defined. 287 * e.g en_cpc:cpc1,cpc2; 288 */ 289 if (hwconfig_f("en_cpc", buffer)) 290 have_hwconfig = true; 291 } 292 293 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 294 if (have_hwconfig) { 295 sprintf(cpc_subarg, "cpc%u", i + 1); 296 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); 297 if (cpc_args == 0) 298 continue; 299 } 300 cpccfg0 = in_be32(&cpc->cpccfg0); 301 size += CPC_CFG0_SZ_K(cpccfg0); 302 303 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 304 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 305 #endif 306 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 307 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 308 #endif 309 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 310 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 311 #endif 312 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 313 if (has_erratum_a006379()) { 314 setbits_be32(&cpc->cpchdbcr0, 315 CPC_HDBCR0_SPLRU_LEVEL_EN); 316 } 317 #endif 318 319 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 320 /* Read back to sync write */ 321 in_be32(&cpc->cpccsr0); 322 323 } 324 325 puts("Corenet Platform Cache: "); 326 print_size(size * 1024, " enabled\n"); 327 } 328 329 static void invalidate_cpc(void) 330 { 331 int i; 332 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 333 334 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 335 /* skip CPC when it used as all SRAM */ 336 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 337 continue; 338 /* Flash invalidate the CPC and clear all the locks */ 339 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 340 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 341 ; 342 } 343 } 344 #else 345 #define enable_cpc() 346 #define invalidate_cpc() 347 #define disable_cpc_sram() 348 #endif /* CONFIG_SYS_FSL_CPC */ 349 350 /* 351 * Breathe some life into the CPU... 352 * 353 * Set up the memory map 354 * initialize a bunch of registers 355 */ 356 357 #ifdef CONFIG_FSL_CORENET 358 static void corenet_tb_init(void) 359 { 360 volatile ccsr_rcpm_t *rcpm = 361 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 362 volatile ccsr_pic_t *pic = 363 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 364 u32 whoami = in_be32(&pic->whoami); 365 366 /* Enable the timebase register for this core */ 367 out_be32(&rcpm->ctbenrl, (1 << whoami)); 368 } 369 #endif 370 371 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 372 void fsl_erratum_a007212_workaround(void) 373 { 374 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 375 u32 ddr_pll_ratio; 376 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); 377 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); 378 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); 379 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 380 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); 381 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); 382 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 383 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); 384 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); 385 #endif 386 #endif 387 /* 388 * Even this workaround applies to selected version of SoCs, it is 389 * safe to apply to all versions, with the limitation of odd ratios. 390 * If RCW has disabled DDR PLL, we have to apply this workaround, 391 * otherwise DDR will not work. 392 */ 393 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 394 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & 395 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 396 /* check if RCW sets ratio to 0, required by this workaround */ 397 if (ddr_pll_ratio != 0) 398 return; 399 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> 400 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & 401 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; 402 /* check if reserved bits have the desired ratio */ 403 if (ddr_pll_ratio == 0) { 404 printf("Error: Unknown DDR PLL ratio!\n"); 405 return; 406 } 407 ddr_pll_ratio >>= 1; 408 409 setbits_be32(plldadcr1, 0x02000001); 410 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 411 setbits_be32(plldadcr2, 0x02000001); 412 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 413 setbits_be32(plldadcr3, 0x02000001); 414 #endif 415 #endif 416 setbits_be32(dpdovrcr4, 0xe0000000); 417 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); 418 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 419 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); 420 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 421 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); 422 #endif 423 #endif 424 udelay(100); 425 clrbits_be32(plldadcr1, 0x02000001); 426 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) 427 clrbits_be32(plldadcr2, 0x02000001); 428 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) 429 clrbits_be32(plldadcr3, 0x02000001); 430 #endif 431 #endif 432 clrbits_be32(dpdovrcr4, 0xe0000000); 433 } 434 #endif 435 436 ulong cpu_init_f(void) 437 { 438 extern void m8560_cpm_reset (void); 439 #ifdef CONFIG_SYS_DCSRBAR_PHYS 440 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 441 #endif 442 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) 443 struct law_entry law; 444 #endif 445 #ifdef CONFIG_ARCH_MPC8548 446 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 447 uint svr = get_svr(); 448 449 /* 450 * CPU2 errata workaround: A core hang possible while executing 451 * a msync instruction and a snoopable transaction from an I/O 452 * master tagged to make quick forward progress is present. 453 * Fixed in silicon rev 2.1. 454 */ 455 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 456 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 457 #endif 458 459 disable_tlb(14); 460 disable_tlb(15); 461 462 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) 463 /* Disable the LAW created for NOR flash by the PBI commands */ 464 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 465 if (law.index != -1) 466 disable_law(law.index); 467 468 #if defined(CONFIG_SYS_CPC_REINIT_F) 469 disable_cpc_sram(); 470 #endif 471 #endif 472 473 #ifdef CONFIG_CPM2 474 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 475 #endif 476 477 init_early_memctl_regs(); 478 479 #if defined(CONFIG_CPM2) 480 m8560_cpm_reset(); 481 #endif 482 483 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) 484 /* Config QE ioports */ 485 config_qe_ioports(); 486 #endif 487 488 #if defined(CONFIG_FSL_DMA) 489 dma_init(); 490 #endif 491 #ifdef CONFIG_FSL_CORENET 492 corenet_tb_init(); 493 #endif 494 init_used_tlb_cams(); 495 496 /* Invalidate the CPC before DDR gets enabled */ 497 invalidate_cpc(); 498 499 #ifdef CONFIG_SYS_DCSRBAR_PHYS 500 /* set DCSRCR so that DCSR space is 1G */ 501 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 502 in_be32(&gur->dcsrcr); 503 #endif 504 505 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 506 fsl_erratum_a007212_workaround(); 507 #endif 508 509 return 0; 510 } 511 512 /* Implement a dummy function for those platforms w/o SERDES */ 513 static void __fsl_serdes__init(void) 514 { 515 return ; 516 } 517 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 518 519 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 520 int enable_cluster_l2(void) 521 { 522 int i = 0; 523 u32 cluster, svr = get_svr(); 524 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 525 struct ccsr_cluster_l2 __iomem *l2cache; 526 527 /* only the L2 of first cluster should be enabled as expected on T4080, 528 * but there is no EOC in the first cluster as HW sake, so return here 529 * to skip enabling L2 cache of the 2nd cluster. 530 */ 531 if (SVR_SOC_VER(svr) == SVR_T4080) 532 return 0; 533 534 cluster = in_be32(&gur->tp_cluster[i].lower); 535 if (cluster & TP_CLUSTER_EOC) 536 return 0; 537 538 /* The first cache has already been set up, so skip it */ 539 i++; 540 541 /* Look through the remaining clusters, and set up their caches */ 542 do { 543 int j, cluster_valid = 0; 544 545 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 546 547 cluster = in_be32(&gur->tp_cluster[i].lower); 548 549 /* check that at least one core/accel is enabled in cluster */ 550 for (j = 0; j < 4; j++) { 551 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 552 u32 type = in_be32(&gur->tp_ityp[idx]); 553 554 if ((type & TP_ITYP_AV) && 555 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) 556 cluster_valid = 1; 557 } 558 559 if (cluster_valid) { 560 /* set stash ID to (cluster) * 2 + 32 + 1 */ 561 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 562 563 printf("enable l2 for cluster %d %p\n", i, l2cache); 564 565 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 566 while ((in_be32(&l2cache->l2csr0) 567 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 568 ; 569 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 570 } 571 i++; 572 } while (!(cluster & TP_CLUSTER_EOC)); 573 574 return 0; 575 } 576 #endif 577 578 /* 579 * Initialize L2 as cache. 580 */ 581 int l2cache_init(void) 582 { 583 __maybe_unused u32 svr = get_svr(); 584 #ifdef CONFIG_L2_CACHE 585 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 586 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 587 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 588 #endif 589 590 puts ("L2: "); 591 592 #if defined(CONFIG_L2_CACHE) 593 volatile uint cache_ctl; 594 uint ver; 595 u32 l2siz_field; 596 597 ver = SVR_SOC_VER(svr); 598 599 asm("msync;isync"); 600 cache_ctl = l2cache->l2ctl; 601 602 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 603 if (cache_ctl & MPC85xx_L2CTL_L2E) { 604 /* Clear L2 SRAM memory-mapped base address */ 605 out_be32(&l2cache->l2srbar0, 0x0); 606 out_be32(&l2cache->l2srbar1, 0x0); 607 608 /* set MBECCDIS=0, SBECCDIS=0 */ 609 clrbits_be32(&l2cache->l2errdis, 610 (MPC85xx_L2ERRDIS_MBECC | 611 MPC85xx_L2ERRDIS_SBECC)); 612 613 /* set L2E=0, L2SRAM=0 */ 614 clrbits_be32(&l2cache->l2ctl, 615 (MPC85xx_L2CTL_L2E | 616 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 617 } 618 #endif 619 620 l2siz_field = (cache_ctl >> 28) & 0x3; 621 622 switch (l2siz_field) { 623 case 0x0: 624 printf(" unknown size (0x%08x)\n", cache_ctl); 625 return -1; 626 break; 627 case 0x1: 628 if (ver == SVR_8540 || ver == SVR_8560 || 629 ver == SVR_8541 || ver == SVR_8555) { 630 puts("128 KiB "); 631 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 632 cache_ctl = 0xc4000000; 633 } else { 634 puts("256 KiB "); 635 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 636 } 637 break; 638 case 0x2: 639 if (ver == SVR_8540 || ver == SVR_8560 || 640 ver == SVR_8541 || ver == SVR_8555) { 641 puts("256 KiB "); 642 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 643 cache_ctl = 0xc8000000; 644 } else { 645 puts("512 KiB "); 646 /* set L2E=1, L2I=1, & L2SRAM=0 */ 647 cache_ctl = 0xc0000000; 648 } 649 break; 650 case 0x3: 651 puts("1024 KiB "); 652 /* set L2E=1, L2I=1, & L2SRAM=0 */ 653 cache_ctl = 0xc0000000; 654 break; 655 } 656 657 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 658 puts("already enabled"); 659 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 660 u32 l2srbar = l2cache->l2srbar0; 661 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 662 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 663 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 664 l2cache->l2srbar0 = l2srbar; 665 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 666 } 667 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 668 puts("\n"); 669 } else { 670 asm("msync;isync"); 671 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 672 asm("msync;isync"); 673 puts("enabled\n"); 674 } 675 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 676 if (SVR_SOC_VER(svr) == SVR_P2040) { 677 puts("N/A\n"); 678 goto skip_l2; 679 } 680 681 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 682 683 /* invalidate the L2 cache */ 684 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 685 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 686 ; 687 688 #ifdef CONFIG_SYS_CACHE_STASHING 689 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 690 mtspr(SPRN_L2CSR1, (32 + 1)); 691 #endif 692 693 /* enable the cache */ 694 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 695 696 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 697 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 698 ; 699 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 700 } 701 702 skip_l2: 703 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 704 if (l2cache->l2csr0 & L2CSR0_L2E) 705 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 706 " enabled\n"); 707 708 enable_cluster_l2(); 709 #else 710 puts("disabled\n"); 711 #endif 712 713 return 0; 714 } 715 716 /* 717 * 718 * The newer 8548, etc, parts have twice as much cache, but 719 * use the same bit-encoding as the older 8555, etc, parts. 720 * 721 */ 722 int cpu_init_r(void) 723 { 724 __maybe_unused u32 svr = get_svr(); 725 #ifdef CONFIG_SYS_LBC_LCRR 726 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 727 #endif 728 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 729 extern int spin_table_compat; 730 const char *spin; 731 #endif 732 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 733 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 734 #endif 735 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 736 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 737 /* 738 * CPU22 and NMG_CPU_A011 share the same workaround. 739 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 740 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 741 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 742 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 743 * be disabled by hwconfig with syntax: 744 * 745 * fsl_cpu_a011:disable 746 */ 747 extern int enable_cpu_a011_workaround; 748 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 749 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 750 #else 751 char buffer[HWCONFIG_BUFFER_SIZE]; 752 char *buf = NULL; 753 int n, res; 754 755 n = env_get_f("hwconfig", buffer, sizeof(buffer)); 756 if (n > 0) 757 buf = buffer; 758 759 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 760 if (res > 0) { 761 enable_cpu_a011_workaround = 0; 762 } else { 763 if (n >= HWCONFIG_BUFFER_SIZE) { 764 printf("fsl_cpu_a011 was not found. hwconfig variable " 765 "may be too long\n"); 766 } 767 enable_cpu_a011_workaround = 768 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 769 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 770 } 771 #endif 772 if (enable_cpu_a011_workaround) { 773 flush_dcache(); 774 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 775 sync(); 776 } 777 #endif 778 779 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907 780 flush_dcache(); 781 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); 782 sync(); 783 #endif 784 785 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 786 /* 787 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 788 * in write shadow mode. Checking DCWS before setting SPR 976. 789 */ 790 if (mfspr(L1CSR2) & L1CSR2_DCWS) 791 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 792 #endif 793 794 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 795 spin = env_get("spin_table_compat"); 796 if (spin && (*spin == 'n')) 797 spin_table_compat = 0; 798 else 799 spin_table_compat = 1; 800 #endif 801 802 #ifdef CONFIG_FSL_CORENET 803 set_liodns(); 804 #ifdef CONFIG_SYS_DPAA_QBMAN 805 setup_qbman_portals(); 806 #endif 807 #endif 808 809 l2cache_init(); 810 #if defined(CONFIG_RAMBOOT_PBL) 811 disable_cpc_sram(); 812 #endif 813 enable_cpc(); 814 #if defined(T1040_TDM_QUIRK_CCSR_BASE) 815 enable_tdm_law(); 816 #endif 817 818 #ifndef CONFIG_SYS_FSL_NO_SERDES 819 /* needs to be in ram since code uses global static vars */ 820 fsl_serdes_init(); 821 #endif 822 823 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 824 #define MCFGR_AXIPIPE 0x000000f0 825 if (IS_SVR_REV(svr, 1, 0)) 826 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); 827 #endif 828 829 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 830 if (IS_SVR_REV(svr, 1, 0)) { 831 int i; 832 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 833 834 for (i = 0; i < 12; i++) { 835 p += i + (i > 5 ? 11 : 0); 836 out_be32(p, 0x2); 837 } 838 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 839 out_be32(p, 0x34); 840 } 841 #endif 842 843 #ifdef CONFIG_SYS_SRIO 844 srio_init(); 845 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 846 char *s = env_get("bootmaster"); 847 if (s) { 848 if (!strcmp(s, "SRIO1")) { 849 srio_boot_master(1); 850 srio_boot_master_release_slave(1); 851 } 852 if (!strcmp(s, "SRIO2")) { 853 srio_boot_master(2); 854 srio_boot_master_release_slave(2); 855 } 856 } 857 #endif 858 #endif 859 860 #if defined(CONFIG_MP) 861 setup_mp(); 862 #endif 863 864 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 865 { 866 if (SVR_MAJ(svr) < 3) { 867 void *p; 868 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 869 setbits_be32(p, 1 << (31 - 14)); 870 } 871 } 872 #endif 873 874 #ifdef CONFIG_SYS_LBC_LCRR 875 /* 876 * Modify the CLKDIV field of LCRR register to improve the writing 877 * speed for NOR flash. 878 */ 879 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 880 __raw_readl(&lbc->lcrr); 881 isync(); 882 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 883 udelay(100); 884 #endif 885 #endif 886 887 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 888 { 889 struct ccsr_usb_phy __iomem *usb_phy1 = 890 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 891 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 892 if (has_erratum_a006261()) 893 fsl_erratum_a006261_workaround(usb_phy1); 894 #endif 895 out_be32(&usb_phy1->usb_enable_override, 896 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 897 } 898 #endif 899 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 900 { 901 struct ccsr_usb_phy __iomem *usb_phy2 = 902 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 903 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 904 if (has_erratum_a006261()) 905 fsl_erratum_a006261_workaround(usb_phy2); 906 #endif 907 out_be32(&usb_phy2->usb_enable_override, 908 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 909 } 910 #endif 911 912 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 913 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 914 * multi-bit ECC errors which has impact on performance, so software 915 * should disable all ECC reporting from USB1 and USB2. 916 */ 917 if (IS_SVR_REV(get_svr(), 1, 0)) { 918 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 919 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 920 setbits_be32(&dcfg->ecccr1, 921 (DCSR_DCFG_ECC_DISABLE_USB1 | 922 DCSR_DCFG_ECC_DISABLE_USB2)); 923 } 924 #endif 925 926 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 927 struct ccsr_usb_phy __iomem *usb_phy = 928 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 929 setbits_be32(&usb_phy->pllprg[1], 930 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 931 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 932 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 933 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 934 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 935 usb_single_source_clk_configure(usb_phy); 936 #endif 937 setbits_be32(&usb_phy->port1.ctrl, 938 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 939 setbits_be32(&usb_phy->port1.drvvbuscfg, 940 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 941 setbits_be32(&usb_phy->port1.pwrfltcfg, 942 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 943 setbits_be32(&usb_phy->port2.ctrl, 944 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 945 setbits_be32(&usb_phy->port2.drvvbuscfg, 946 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 947 setbits_be32(&usb_phy->port2.pwrfltcfg, 948 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 949 950 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 951 if (has_erratum_a006261()) 952 fsl_erratum_a006261_workaround(usb_phy); 953 #endif 954 955 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ 956 957 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 958 erratum_a009942_check_cpo(); 959 #endif 960 961 #ifdef CONFIG_FMAN_ENET 962 fman_enet_init(); 963 #endif 964 965 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) 966 if (pamu_init() < 0) 967 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); 968 #endif 969 970 #ifdef CONFIG_FSL_CAAM 971 sec_init(); 972 973 #if defined(CONFIG_ARCH_C29X) 974 if ((SVR_SOC_VER(svr) == SVR_C292) || 975 (SVR_SOC_VER(svr) == SVR_C293)) 976 sec_init_idx(1); 977 978 if (SVR_SOC_VER(svr) == SVR_C293) 979 sec_init_idx(2); 980 #endif 981 #endif 982 983 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) 984 /* 985 * For P1022/1013 Rev1.0 silicon, after power on SATA host 986 * controller is configured in legacy mode instead of the 987 * expected enterprise mode. Software needs to clear bit[28] 988 * of HControl register to change to enterprise mode from 989 * legacy mode. We assume that the controller is offline. 990 */ 991 if (IS_SVR_REV(svr, 1, 0) && 992 ((SVR_SOC_VER(svr) == SVR_P1022) || 993 (SVR_SOC_VER(svr) == SVR_P1013))) { 994 fsl_sata_reg_t *reg; 995 996 /* first SATA controller */ 997 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 998 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 999 1000 /* second SATA controller */ 1001 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 1002 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); 1003 } 1004 #endif 1005 1006 init_used_tlb_cams(); 1007 1008 return 0; 1009 } 1010 1011 void arch_preboot_os(void) 1012 { 1013 u32 msr; 1014 1015 /* 1016 * We are changing interrupt offsets and are about to boot the OS so 1017 * we need to make sure we disable all async interrupts. EE is already 1018 * disabled by the time we get called. 1019 */ 1020 msr = mfmsr(); 1021 msr &= ~(MSR_ME|MSR_CE); 1022 mtmsr(msr); 1023 } 1024 1025 #if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA) 1026 int sata_initialize(void) 1027 { 1028 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 1029 return __sata_initialize(); 1030 1031 return 1; 1032 } 1033 #endif 1034 1035 void cpu_secondary_init_r(void) 1036 { 1037 #ifdef CONFIG_U_QE 1038 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ 1039 #elif defined CONFIG_QE 1040 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 1041 #endif 1042 1043 #ifdef CONFIG_QE 1044 qe_init(qe_base); 1045 qe_reset(); 1046 #endif 1047 } 1048 1049 #ifdef CONFIG_BOARD_LATE_INIT 1050 int board_late_init(void) 1051 { 1052 #ifdef CONFIG_CHAIN_OF_TRUST 1053 fsl_setenv_chain_of_trust(); 1054 #endif 1055 1056 return 0; 1057 } 1058 #endif 1059
