1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 16 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMBaseRegisterInfo.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMFrameLowering.h" 21 #include "ARMISelLowering.h" 22 #include "ARMSelectionDAGInfo.h" 23 #include "llvm/ADT/Triple.h" 24 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 26 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 27 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include "llvm/MC/MCInstrItineraries.h" 31 #include "llvm/MC/MCSchedule.h" 32 #include "llvm/Target/TargetOptions.h" 33 #include <memory> 34 #include <string> 35 36 #define GET_SUBTARGETINFO_HEADER 37 #include "ARMGenSubtargetInfo.inc" 38 39 namespace llvm { 40 41 class ARMBaseTargetMachine; 42 class GlobalValue; 43 class StringRef; 44 45 class ARMSubtarget : public ARMGenSubtargetInfo { 46 protected: 47 enum ARMProcFamilyEnum { 48 Others, 49 50 CortexA12, 51 CortexA15, 52 CortexA17, 53 CortexA32, 54 CortexA35, 55 CortexA5, 56 CortexA53, 57 CortexA55, 58 CortexA57, 59 CortexA7, 60 CortexA72, 61 CortexA73, 62 CortexA75, 63 CortexA8, 64 CortexA9, 65 CortexM3, 66 CortexR4, 67 CortexR4F, 68 CortexR5, 69 CortexR52, 70 CortexR7, 71 ExynosM1, 72 Krait, 73 Kryo, 74 Swift 75 }; 76 enum ARMProcClassEnum { 77 None, 78 79 AClass, 80 MClass, 81 RClass 82 }; 83 enum ARMArchEnum { 84 ARMv2, 85 ARMv2a, 86 ARMv3, 87 ARMv3m, 88 ARMv4, 89 ARMv4t, 90 ARMv5, 91 ARMv5t, 92 ARMv5te, 93 ARMv5tej, 94 ARMv6, 95 ARMv6k, 96 ARMv6kz, 97 ARMv6m, 98 ARMv6sm, 99 ARMv6t2, 100 ARMv7a, 101 ARMv7em, 102 ARMv7m, 103 ARMv7r, 104 ARMv7ve, 105 ARMv81a, 106 ARMv82a, 107 ARMv83a, 108 ARMv84a, 109 ARMv8a, 110 ARMv8mBaseline, 111 ARMv8mMainline, 112 ARMv8r 113 }; 114 115 public: 116 /// What kind of timing do load multiple/store multiple instructions have. 117 enum ARMLdStMultipleTiming { 118 /// Can load/store 2 registers/cycle. 119 DoubleIssue, 120 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access 121 /// is not 64-bit aligned. 122 DoubleIssueCheckUnalignedAccess, 123 /// Can load/store 1 register/cycle. 124 SingleIssue, 125 /// Can load/store 1 register/cycle, but needs an extra cycle for address 126 /// computation and potentially also for register writeback. 127 SingleIssuePlusExtras, 128 }; 129 130 protected: 131 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 132 ARMProcFamilyEnum ARMProcFamily = Others; 133 134 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 135 ARMProcClassEnum ARMProcClass = None; 136 137 /// ARMArch - ARM architecture 138 ARMArchEnum ARMArch = ARMv4t; 139 140 /// HasV4TOps, HasV5TOps, HasV5TEOps, 141 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - 142 /// Specify whether target support specific ARM ISA variants. 143 bool HasV4TOps = false; 144 bool HasV5TOps = false; 145 bool HasV5TEOps = false; 146 bool HasV6Ops = false; 147 bool HasV6MOps = false; 148 bool HasV6KOps = false; 149 bool HasV6T2Ops = false; 150 bool HasV7Ops = false; 151 bool HasV8Ops = false; 152 bool HasV8_1aOps = false; 153 bool HasV8_2aOps = false; 154 bool HasV8_3aOps = false; 155 bool HasV8_4aOps = false; 156 bool HasV8MBaselineOps = false; 157 bool HasV8MMainlineOps = false; 158 159 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what 160 /// floating point ISAs are supported. 161 bool HasVFPv2 = false; 162 bool HasVFPv3 = false; 163 bool HasVFPv4 = false; 164 bool HasFPARMv8 = false; 165 bool HasNEON = false; 166 167 /// HasDotProd - True if the ARMv8.2A dot product instructions are supported. 168 bool HasDotProd = false; 169 170 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 171 /// specified. Use the method useNEONForSinglePrecisionFP() to 172 /// determine if NEON should actually be used. 173 bool UseNEONForSinglePrecisionFP = false; 174 175 /// UseMulOps - True if non-microcoded fused integer multiply-add and 176 /// multiply-subtract instructions should be used. 177 bool UseMulOps = false; 178 179 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 180 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 181 bool SlowFPVMLx = false; 182 183 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 184 /// forwarding to allow mul + mla being issued back to back. 185 bool HasVMLxForwarding = false; 186 187 /// SlowFPBrcc - True if floating point compare + branch is slow. 188 bool SlowFPBrcc = false; 189 190 /// InThumbMode - True if compiling for Thumb, false for ARM. 191 bool InThumbMode = false; 192 193 /// UseSoftFloat - True if we're using software floating point features. 194 bool UseSoftFloat = false; 195 196 /// UseMISched - True if MachineScheduler should be used for this subtarget. 197 bool UseMISched = false; 198 199 /// DisablePostRAScheduler - False if scheduling should happen again after 200 /// register allocation. 201 bool DisablePostRAScheduler = false; 202 203 /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc) 204 bool UseAA = false; 205 206 /// HasThumb2 - True if Thumb2 instructions are supported. 207 bool HasThumb2 = false; 208 209 /// NoARM - True if subtarget does not support ARM mode execution. 210 bool NoARM = false; 211 212 /// ReserveR9 - True if R9 is not available as a general purpose register. 213 bool ReserveR9 = false; 214 215 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of 216 /// 32-bit imms (including global addresses). 217 bool NoMovt = false; 218 219 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 220 /// must be able to synthesize call stubs for interworking between ARM and 221 /// Thumb. 222 bool SupportsTailCall = false; 223 224 /// HasFP16 - True if subtarget supports half-precision FP conversions 225 bool HasFP16 = false; 226 227 /// HasFullFP16 - True if subtarget supports half-precision FP operations 228 bool HasFullFP16 = false; 229 230 /// HasD16 - True if subtarget is limited to 16 double precision 231 /// FP registers for VFPv3. 232 bool HasD16 = false; 233 234 /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode 235 bool HasHardwareDivideInThumb = false; 236 237 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 238 bool HasHardwareDivideInARM = false; 239 240 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 241 /// instructions. 242 bool HasDataBarrier = false; 243 244 /// HasFullDataBarrier - True if the subtarget supports DFB data barrier 245 /// instruction. 246 bool HasFullDataBarrier = false; 247 248 /// HasV7Clrex - True if the subtarget supports CLREX instructions 249 bool HasV7Clrex = false; 250 251 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) 252 /// instructions 253 bool HasAcquireRelease = false; 254 255 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 256 /// over 16-bit ones. 257 bool Pref32BitThumb = false; 258 259 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 260 /// that partially update CPSR and add false dependency on the previous 261 /// CPSR setting instruction. 262 bool AvoidCPSRPartialUpdate = false; 263 264 /// CheapPredicableCPSRDef - If true, disable +1 predication cost 265 /// for instructions updating CPSR. Enabled for Cortex-A57. 266 bool CheapPredicableCPSRDef = false; 267 268 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting 269 /// movs with shifter operand (i.e. asr, lsl, lsr). 270 bool AvoidMOVsShifterOperand = false; 271 272 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should 273 /// avoid issue "normal" call instructions to callees which do not return. 274 bool HasRetAddrStack = false; 275 276 /// HasBranchPredictor - True if the subtarget has a branch predictor. Having 277 /// a branch predictor or not changes the expected cost of taking a branch 278 /// which affects the choice of whether to use predicated instructions. 279 bool HasBranchPredictor = true; 280 281 /// HasMPExtension - True if the subtarget supports Multiprocessing 282 /// extension (ARMv7 only). 283 bool HasMPExtension = false; 284 285 /// HasVirtualization - True if the subtarget supports the Virtualization 286 /// extension. 287 bool HasVirtualization = false; 288 289 /// FPOnlySP - If true, the floating point unit only supports single 290 /// precision. 291 bool FPOnlySP = false; 292 293 /// If true, the processor supports the Performance Monitor Extensions. These 294 /// include a generic cycle-counter as well as more fine-grained (often 295 /// implementation-specific) events. 296 bool HasPerfMon = false; 297 298 /// HasTrustZone - if true, processor supports TrustZone security extensions 299 bool HasTrustZone = false; 300 301 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions 302 bool Has8MSecExt = false; 303 304 /// HasSHA2 - if true, processor supports SHA1 and SHA256 305 bool HasSHA2 = false; 306 307 /// HasAES - if true, processor supports AES 308 bool HasAES = false; 309 310 /// HasCrypto - if true, processor supports Cryptography extensions 311 bool HasCrypto = false; 312 313 /// HasCRC - if true, processor supports CRC instructions 314 bool HasCRC = false; 315 316 /// HasRAS - if true, the processor supports RAS extensions 317 bool HasRAS = false; 318 319 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are 320 /// particularly effective at zeroing a VFP register. 321 bool HasZeroCycleZeroing = false; 322 323 /// HasFPAO - if true, processor does positive address offset computation faster 324 bool HasFPAO = false; 325 326 /// HasFuseAES - if true, processor executes back to back AES instruction 327 /// pairs faster. 328 bool HasFuseAES = false; 329 330 /// HasFuseLiterals - if true, processor executes back to back 331 /// bottom and top halves of literal generation faster. 332 bool HasFuseLiterals = false; 333 334 /// If true, if conversion may decide to leave some instructions unpredicated. 335 bool IsProfitableToUnpredicate = false; 336 337 /// If true, VMOV will be favored over VGETLNi32. 338 bool HasSlowVGETLNi32 = false; 339 340 /// If true, VMOV will be favored over VDUP. 341 bool HasSlowVDUP32 = false; 342 343 /// If true, VMOVSR will be favored over VMOVDRR. 344 bool PreferVMOVSR = false; 345 346 /// If true, ISHST barriers will be used for Release semantics. 347 bool PreferISHST = false; 348 349 /// If true, a VLDM/VSTM starting with an odd register number is considered to 350 /// take more microops than single VLDRS/VSTRS. 351 bool SlowOddRegister = false; 352 353 /// If true, loading into a D subregister will be penalized. 354 bool SlowLoadDSubregister = false; 355 356 /// If true, the AGU and NEON/FPU units are multiplexed. 357 bool HasMuxedUnits = false; 358 359 /// If true, VMOVS will never be widened to VMOVD. 360 bool DontWidenVMOVS = false; 361 362 /// If true, splat a register between VFP and NEON instructions. 363 bool SplatVFPToNeon = false; 364 365 /// If true, run the MLx expansion pass. 366 bool ExpandMLx = false; 367 368 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards. 369 bool HasVMLxHazards = false; 370 371 // If true, read thread pointer from coprocessor register. 372 bool ReadTPHard = false; 373 374 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. 375 bool UseNEONForFPMovs = false; 376 377 /// If true, VLDn instructions take an extra cycle for unaligned accesses. 378 bool CheckVLDnAlign = false; 379 380 /// If true, VFP instructions are not pipelined. 381 bool NonpipelinedVFP = false; 382 383 /// StrictAlign - If true, the subtarget disallows unaligned memory 384 /// accesses for some types. For details, see 385 /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). 386 bool StrictAlign = false; 387 388 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT 389 /// blocks to conform to ARMv8 rule. 390 bool RestrictIT = false; 391 392 /// HasDSP - If true, the subtarget supports the DSP (saturating arith 393 /// and such) instructions. 394 bool HasDSP = false; 395 396 /// NaCl TRAP instruction is generated instead of the regular TRAP. 397 bool UseNaClTrap = false; 398 399 /// Generate calls via indirect call instructions. 400 bool GenLongCalls = false; 401 402 /// Generate code that does not contain data access to code sections. 403 bool GenExecuteOnly = false; 404 405 /// Target machine allowed unsafe FP math (such as use of NEON fp) 406 bool UnsafeFPMath = false; 407 408 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). 409 bool UseSjLjEH = false; 410 411 /// Implicitly convert an instruction to a different one if its immediates 412 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1. 413 bool NegativeImmediates = true; 414 415 /// stackAlignment - The minimum alignment known to hold of the stack frame on 416 /// entry to the function and which must be maintained by every function. 417 unsigned stackAlignment = 4; 418 419 /// CPUString - String name of used CPU. 420 std::string CPUString; 421 422 unsigned MaxInterleaveFactor = 1; 423 424 /// Clearance before partial register updates (in number of instructions) 425 unsigned PartialUpdateClearance = 0; 426 427 /// What kind of timing do load multiple/store multiple have (double issue, 428 /// single issue etc). 429 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue; 430 431 /// The adjustment that we need to apply to get the operand latency from the 432 /// operand cycle returned by the itinerary data for pre-ISel operands. 433 int PreISelOperandLatencyAdjustment = 2; 434 435 /// IsLittle - The target is Little Endian 436 bool IsLittle; 437 438 /// TargetTriple - What processor and OS we're targeting. 439 Triple TargetTriple; 440 441 /// SchedModel - Processor specific instruction costs. 442 MCSchedModel SchedModel; 443 444 /// Selected instruction itineraries (one entry per itinerary class.) 445 InstrItineraryData InstrItins; 446 447 /// Options passed via command line that could influence the target 448 const TargetOptions &Options; 449 450 const ARMBaseTargetMachine &TM; 451 452 public: 453 /// This constructor initializes the data members to match that 454 /// of the specified triple. 455 /// 456 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 457 const ARMBaseTargetMachine &TM, bool IsLittle); 458 459 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 460 /// that still makes it profitable to inline the call. 461 unsigned getMaxInlineSizeThreshold() const { 462 return 64; 463 } 464 465 /// ParseSubtargetFeatures - Parses features string setting specified 466 /// subtarget options. Definition of function is auto generated by tblgen. 467 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 468 469 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 470 /// so that we can use initializer lists for subtarget initialization. 471 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 472 473 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 474 return &TSInfo; 475 } 476 477 const ARMBaseInstrInfo *getInstrInfo() const override { 478 return InstrInfo.get(); 479 } 480 481 const ARMTargetLowering *getTargetLowering() const override { 482 return &TLInfo; 483 } 484 485 const ARMFrameLowering *getFrameLowering() const override { 486 return FrameLowering.get(); 487 } 488 489 const ARMBaseRegisterInfo *getRegisterInfo() const override { 490 return &InstrInfo->getRegisterInfo(); 491 } 492 493 const CallLowering *getCallLowering() const override; 494 const InstructionSelector *getInstructionSelector() const override; 495 const LegalizerInfo *getLegalizerInfo() const override; 496 const RegisterBankInfo *getRegBankInfo() const override; 497 498 private: 499 ARMSelectionDAGInfo TSInfo; 500 // Either Thumb1FrameLowering or ARMFrameLowering. 501 std::unique_ptr<ARMFrameLowering> FrameLowering; 502 // Either Thumb1InstrInfo or Thumb2InstrInfo. 503 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 504 ARMTargetLowering TLInfo; 505 506 /// GlobalISel related APIs. 507 std::unique_ptr<CallLowering> CallLoweringInfo; 508 std::unique_ptr<InstructionSelector> InstSelector; 509 std::unique_ptr<LegalizerInfo> Legalizer; 510 std::unique_ptr<RegisterBankInfo> RegBankInfo; 511 512 void initializeEnvironment(); 513 void initSubtargetFeatures(StringRef CPU, StringRef FS); 514 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 515 516 public: 517 void computeIssueWidth(); 518 519 bool hasV4TOps() const { return HasV4TOps; } 520 bool hasV5TOps() const { return HasV5TOps; } 521 bool hasV5TEOps() const { return HasV5TEOps; } 522 bool hasV6Ops() const { return HasV6Ops; } 523 bool hasV6MOps() const { return HasV6MOps; } 524 bool hasV6KOps() const { return HasV6KOps; } 525 bool hasV6T2Ops() const { return HasV6T2Ops; } 526 bool hasV7Ops() const { return HasV7Ops; } 527 bool hasV8Ops() const { return HasV8Ops; } 528 bool hasV8_1aOps() const { return HasV8_1aOps; } 529 bool hasV8_2aOps() const { return HasV8_2aOps; } 530 bool hasV8_3aOps() const { return HasV8_3aOps; } 531 bool hasV8_4aOps() const { return HasV8_4aOps; } 532 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } 533 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } 534 535 /// @{ 536 /// These functions are obsolete, please consider adding subtarget features 537 /// or properties instead of calling them. 538 bool isCortexA5() const { return ARMProcFamily == CortexA5; } 539 bool isCortexA7() const { return ARMProcFamily == CortexA7; } 540 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 541 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 542 bool isCortexA15() const { return ARMProcFamily == CortexA15; } 543 bool isSwift() const { return ARMProcFamily == Swift; } 544 bool isCortexM3() const { return ARMProcFamily == CortexM3; } 545 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } 546 bool isCortexR5() const { return ARMProcFamily == CortexR5; } 547 bool isKrait() const { return ARMProcFamily == Krait; } 548 /// @} 549 550 bool hasARMOps() const { return !NoARM; } 551 552 bool hasVFP2() const { return HasVFPv2; } 553 bool hasVFP3() const { return HasVFPv3; } 554 bool hasVFP4() const { return HasVFPv4; } 555 bool hasFPARMv8() const { return HasFPARMv8; } 556 bool hasNEON() const { return HasNEON; } 557 bool hasSHA2() const { return HasSHA2; } 558 bool hasAES() const { return HasAES; } 559 bool hasCrypto() const { return HasCrypto; } 560 bool hasDotProd() const { return HasDotProd; } 561 bool hasCRC() const { return HasCRC; } 562 bool hasRAS() const { return HasRAS; } 563 bool hasVirtualization() const { return HasVirtualization; } 564 565 bool useNEONForSinglePrecisionFP() const { 566 return hasNEON() && UseNEONForSinglePrecisionFP; 567 } 568 569 bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; } 570 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } 571 bool hasDataBarrier() const { return HasDataBarrier; } 572 bool hasFullDataBarrier() const { return HasFullDataBarrier; } 573 bool hasV7Clrex() const { return HasV7Clrex; } 574 bool hasAcquireRelease() const { return HasAcquireRelease; } 575 576 bool hasAnyDataBarrier() const { 577 return HasDataBarrier || (hasV6Ops() && !isThumb()); 578 } 579 580 bool useMulOps() const { return UseMulOps; } 581 bool useFPVMLx() const { return !SlowFPVMLx; } 582 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 583 bool isFPBrccSlow() const { return SlowFPBrcc; } 584 bool isFPOnlySP() const { return FPOnlySP; } 585 bool hasPerfMon() const { return HasPerfMon; } 586 bool hasTrustZone() const { return HasTrustZone; } 587 bool has8MSecExt() const { return Has8MSecExt; } 588 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } 589 bool hasFPAO() const { return HasFPAO; } 590 bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; } 591 bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; } 592 bool hasSlowVDUP32() const { return HasSlowVDUP32; } 593 bool preferVMOVSR() const { return PreferVMOVSR; } 594 bool preferISHSTBarriers() const { return PreferISHST; } 595 bool expandMLx() const { return ExpandMLx; } 596 bool hasVMLxHazards() const { return HasVMLxHazards; } 597 bool hasSlowOddRegister() const { return SlowOddRegister; } 598 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; } 599 bool hasMuxedUnits() const { return HasMuxedUnits; } 600 bool dontWidenVMOVS() const { return DontWidenVMOVS; } 601 bool useSplatVFPToNeon() const { return SplatVFPToNeon; } 602 bool useNEONForFPMovs() const { return UseNEONForFPMovs; } 603 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; } 604 bool nonpipelinedVFP() const { return NonpipelinedVFP; } 605 bool prefers32BitThumb() const { return Pref32BitThumb; } 606 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 607 bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; } 608 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } 609 bool hasRetAddrStack() const { return HasRetAddrStack; } 610 bool hasBranchPredictor() const { return HasBranchPredictor; } 611 bool hasMPExtension() const { return HasMPExtension; } 612 bool hasDSP() const { return HasDSP; } 613 bool useNaClTrap() const { return UseNaClTrap; } 614 bool useSjLjEH() const { return UseSjLjEH; } 615 bool genLongCalls() const { return GenLongCalls; } 616 bool genExecuteOnly() const { return GenExecuteOnly; } 617 618 bool hasFP16() const { return HasFP16; } 619 bool hasD16() const { return HasD16; } 620 bool hasFullFP16() const { return HasFullFP16; } 621 622 bool hasFuseAES() const { return HasFuseAES; } 623 bool hasFuseLiterals() const { return HasFuseLiterals; } 624 /// Return true if the CPU supports any kind of instruction fusion. 625 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); } 626 627 const Triple &getTargetTriple() const { return TargetTriple; } 628 629 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 630 bool isTargetIOS() const { return TargetTriple.isiOS(); } 631 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); } 632 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); } 633 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 634 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 635 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } 636 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 637 638 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 639 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 640 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 641 642 // ARM EABI is the bare-metal EABI described in ARM ABI documents and 643 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. 644 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI 645 // even for GNUEABI, so we can make a distinction here and still conform to 646 // the EABI on GNU (and Android) mode. This requires change in Clang, too. 647 // FIXME: The Darwin exception is temporary, while we move users to 648 // "*-*-*-macho" triples as quickly as possible. 649 bool isTargetAEABI() const { 650 return (TargetTriple.getEnvironment() == Triple::EABI || 651 TargetTriple.getEnvironment() == Triple::EABIHF) && 652 !isTargetDarwin() && !isTargetWindows(); 653 } 654 bool isTargetGNUAEABI() const { 655 return (TargetTriple.getEnvironment() == Triple::GNUEABI || 656 TargetTriple.getEnvironment() == Triple::GNUEABIHF) && 657 !isTargetDarwin() && !isTargetWindows(); 658 } 659 bool isTargetMuslAEABI() const { 660 return (TargetTriple.getEnvironment() == Triple::MuslEABI || 661 TargetTriple.getEnvironment() == Triple::MuslEABIHF) && 662 !isTargetDarwin() && !isTargetWindows(); 663 } 664 665 // ARM Targets that support EHABI exception handling standard 666 // Darwin uses SjLj. Other targets might need more checks. 667 bool isTargetEHABICompatible() const { 668 return (TargetTriple.getEnvironment() == Triple::EABI || 669 TargetTriple.getEnvironment() == Triple::GNUEABI || 670 TargetTriple.getEnvironment() == Triple::MuslEABI || 671 TargetTriple.getEnvironment() == Triple::EABIHF || 672 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 673 TargetTriple.getEnvironment() == Triple::MuslEABIHF || 674 isTargetAndroid()) && 675 !isTargetDarwin() && !isTargetWindows(); 676 } 677 678 bool isTargetHardFloat() const; 679 680 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 681 682 bool isXRaySupported() const override; 683 684 bool isAPCS_ABI() const; 685 bool isAAPCS_ABI() const; 686 bool isAAPCS16_ABI() const; 687 688 bool isROPI() const; 689 bool isRWPI() const; 690 691 bool useMachineScheduler() const { return UseMISched; } 692 bool disablePostRAScheduler() const { return DisablePostRAScheduler; } 693 bool useSoftFloat() const { return UseSoftFloat; } 694 bool isThumb() const { return InThumbMode; } 695 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } 696 bool isThumb2() const { return InThumbMode && HasThumb2; } 697 bool hasThumb2() const { return HasThumb2; } 698 bool isMClass() const { return ARMProcClass == MClass; } 699 bool isRClass() const { return ARMProcClass == RClass; } 700 bool isAClass() const { return ARMProcClass == AClass; } 701 bool isReadTPHard() const { return ReadTPHard; } 702 703 bool isR9Reserved() const { 704 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; 705 } 706 707 bool useR7AsFramePointer() const { 708 return isTargetDarwin() || (!isTargetWindows() && isThumb()); 709 } 710 711 /// Returns true if the frame setup is split into two separate pushes (first 712 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent 713 /// to lr. This is always required on Thumb1-only targets, as the push and 714 /// pop instructions can't access the high registers. 715 bool splitFramePushPop(const MachineFunction &MF) const { 716 return (useR7AsFramePointer() && 717 MF.getTarget().Options.DisableFramePointerElim(MF)) || 718 isThumb1Only(); 719 } 720 721 bool useStride4VFPs(const MachineFunction &MF) const; 722 723 bool useMovt(const MachineFunction &MF) const; 724 725 bool supportsTailCall() const { return SupportsTailCall; } 726 727 bool allowsUnalignedMem() const { return !StrictAlign; } 728 729 bool restrictIT() const { return RestrictIT; } 730 731 const std::string & getCPUString() const { return CPUString; } 732 733 bool isLittle() const { return IsLittle; } 734 735 unsigned getMispredictionPenalty() const; 736 737 /// Returns true if machine scheduler should be enabled. 738 bool enableMachineScheduler() const override; 739 740 /// True for some subtargets at > -O0. 741 bool enablePostRAScheduler() const override; 742 743 /// Enable use of alias analysis during code generation (during MI 744 /// scheduling, DAGCombine, etc.). 745 bool useAA() const override { return UseAA; } 746 747 // enableAtomicExpand- True if we need to expand our atomics. 748 bool enableAtomicExpand() const override; 749 750 /// getInstrItins - Return the instruction itineraries based on subtarget 751 /// selection. 752 const InstrItineraryData *getInstrItineraryData() const override { 753 return &InstrItins; 754 } 755 756 /// getStackAlignment - Returns the minimum alignment known to hold of the 757 /// stack frame on entry to the function and which must be maintained by every 758 /// function for this subtarget. 759 unsigned getStackAlignment() const { return stackAlignment; } 760 761 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; } 762 763 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; } 764 765 ARMLdStMultipleTiming getLdStMultipleTiming() const { 766 return LdStMultipleTiming; 767 } 768 769 int getPreISelOperandLatencyAdjustment() const { 770 return PreISelOperandLatencyAdjustment; 771 } 772 773 /// True if the GV will be accessed via an indirect symbol. 774 bool isGVIndirectSymbol(const GlobalValue *GV) const; 775 776 /// Returns the constant pool modifier needed to access the GV. 777 bool isGVInGOT(const GlobalValue *GV) const; 778 779 /// True if fast-isel is used. 780 bool useFastISel() const; 781 782 /// Returns the correct return opcode for the current feature set. 783 /// Use BX if available to allow mixing thumb/arm code, but fall back 784 /// to plain mov pc,lr on ARMv4. 785 unsigned getReturnOpcode() const { 786 if (isThumb()) 787 return ARM::tBX_RET; 788 if (hasV4TOps()) 789 return ARM::BX_RET; 790 return ARM::MOVPCLR; 791 } 792 793 /// Allow movt+movw for PIC global address calculation. 794 /// ELF does not have GOT relocations for movt+movw. 795 /// ROPI does not use GOT. 796 bool allowPositionIndependentMovt() const { 797 return isROPI() || !isTargetELF(); 798 } 799 }; 800 801 } // end namespace llvm 802 803 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 804
