1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "PPCTargetMachine.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/Statistic.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/RegisterScavenging.h" 31 #include "llvm/CodeGen/TargetFrameLowering.h" 32 #include "llvm/CodeGen/TargetInstrInfo.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/Constants.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/IR/Type.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 using namespace llvm; 47 48 #define DEBUG_TYPE "reginfo" 49 50 #define GET_REGINFO_TARGET_DESC 51 #include "PPCGenRegisterInfo.inc" 52 53 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass"); 54 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass"); 55 56 static cl::opt<bool> 57 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 58 cl::desc("Enable use of a base pointer for complex stack frames")); 59 60 static cl::opt<bool> 61 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 62 cl::desc("Force the use of a base pointer in every function")); 63 64 static cl::opt<bool> 65 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false), 66 cl::desc("Enable spills from gpr to vsr rather than stack")); 67 68 static cl::opt<bool> 69 StackPtrConst("ppc-stack-ptr-caller-preserved", 70 cl::desc("Consider R1 caller preserved so stack saves of " 71 "caller preserved registers can be LICM candidates"), 72 cl::init(true), cl::Hidden); 73 74 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) 75 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, 76 TM.isPPC64() ? 0 : 1, 77 TM.isPPC64() ? 0 : 1), 78 TM(TM) { 79 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 80 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 81 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 82 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 83 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 84 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 85 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 86 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 87 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 88 89 // 64-bit 90 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 91 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 92 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 93 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 94 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 95 96 // VSX 97 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX; 98 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX; 99 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX; 100 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX; 101 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX; 102 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX; 103 ImmToIdxMap[PPC::LXV] = PPC::LXVX; 104 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; 105 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX; 106 ImmToIdxMap[PPC::STXV] = PPC::STXVX; 107 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX; 108 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX; 109 110 // SPE 111 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX; 112 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX; 113 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX; 114 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX; 115 } 116 117 /// getPointerRegClass - Return the register class to use to hold pointers. 118 /// This is used for addressing modes. 119 const TargetRegisterClass * 120 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 121 const { 122 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 123 // when it checks for ZERO folding. 124 if (Kind == 1) { 125 if (TM.isPPC64()) 126 return &PPC::G8RC_NOX0RegClass; 127 return &PPC::GPRC_NOR0RegClass; 128 } 129 130 if (TM.isPPC64()) 131 return &PPC::G8RCRegClass; 132 return &PPC::GPRCRegClass; 133 } 134 135 const MCPhysReg* 136 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 137 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 138 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) { 139 if (Subtarget.hasVSX()) 140 return CSR_64_AllRegs_VSX_SaveList; 141 if (Subtarget.hasAltivec()) 142 return CSR_64_AllRegs_Altivec_SaveList; 143 return CSR_64_AllRegs_SaveList; 144 } 145 146 if (Subtarget.isDarwinABI()) 147 return TM.isPPC64() 148 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 149 : CSR_Darwin64_SaveList) 150 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 151 : CSR_Darwin32_SaveList); 152 153 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) 154 return CSR_SRV464_TLS_PE_SaveList; 155 156 if (Subtarget.hasSPE()) 157 return CSR_SVR432_SPE_SaveList; 158 159 // On PPC64, we might need to save r2 (but only if it is not reserved). 160 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 161 162 if (MF->getFunction().getCallingConv() == CallingConv::Cold) { 163 return TM.isPPC64() 164 ? (Subtarget.hasAltivec() 165 ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList 166 : CSR_SVR64_ColdCC_Altivec_SaveList) 167 : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList 168 : CSR_SVR64_ColdCC_SaveList)) 169 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList 170 : CSR_SVR32_ColdCC_SaveList); 171 } 172 173 return TM.isPPC64() 174 ? (Subtarget.hasAltivec() 175 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList 176 : CSR_SVR464_Altivec_SaveList) 177 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList)) 178 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 179 : CSR_SVR432_SaveList); 180 } 181 182 const MCPhysReg * 183 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { 184 assert(MF && "Invalid MachineFunction pointer."); 185 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 186 if (Subtarget.isDarwinABI()) 187 return nullptr; 188 if (!TM.isPPC64()) 189 return nullptr; 190 if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS) 191 return nullptr; 192 if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) 193 return nullptr; 194 195 // On PPC64, we might need to save r2 (but only if it is not reserved). 196 bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2); 197 if (Subtarget.hasAltivec()) 198 return SaveR2 199 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList 200 : CSR_SVR464_Altivec_ViaCopy_SaveList; 201 else 202 return SaveR2 203 ? CSR_SVR464_R2_ViaCopy_SaveList 204 : CSR_SVR464_ViaCopy_SaveList; 205 } 206 207 const uint32_t * 208 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 209 CallingConv::ID CC) const { 210 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 211 if (CC == CallingConv::AnyReg) { 212 if (Subtarget.hasVSX()) 213 return CSR_64_AllRegs_VSX_RegMask; 214 if (Subtarget.hasAltivec()) 215 return CSR_64_AllRegs_Altivec_RegMask; 216 return CSR_64_AllRegs_RegMask; 217 } 218 219 if (Subtarget.isDarwinABI()) 220 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask 221 : CSR_Darwin64_RegMask) 222 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask 223 : CSR_Darwin32_RegMask); 224 225 if (CC == CallingConv::Cold) { 226 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask 227 : CSR_SVR64_ColdCC_RegMask) 228 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask 229 : CSR_SVR32_ColdCC_RegMask); 230 } 231 232 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask 233 : CSR_SVR464_RegMask) 234 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask 235 : CSR_SVR432_RegMask); 236 } 237 238 const uint32_t* 239 PPCRegisterInfo::getNoPreservedMask() const { 240 return CSR_NoRegs_RegMask; 241 } 242 243 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 244 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 245 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 246 } 247 248 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 249 BitVector Reserved(getNumRegs()); 250 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 251 const PPCFrameLowering *TFI = getFrameLowering(MF); 252 253 // The ZERO register is not really a register, but the representation of r0 254 // when used in instructions that treat r0 as the constant 0. 255 markSuperRegs(Reserved, PPC::ZERO); 256 257 // The FP register is also not really a register, but is the representation 258 // of the frame pointer register used by ISD::FRAMEADDR. 259 markSuperRegs(Reserved, PPC::FP); 260 261 // The BP register is also not really a register, but is the representation 262 // of the base pointer register used by setjmp. 263 markSuperRegs(Reserved, PPC::BP); 264 265 // The counter registers must be reserved so that counter-based loops can 266 // be correctly formed (and the mtctr instructions are not DCE'd). 267 markSuperRegs(Reserved, PPC::CTR); 268 markSuperRegs(Reserved, PPC::CTR8); 269 270 markSuperRegs(Reserved, PPC::R1); 271 markSuperRegs(Reserved, PPC::LR); 272 markSuperRegs(Reserved, PPC::LR8); 273 markSuperRegs(Reserved, PPC::RM); 274 275 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 276 markSuperRegs(Reserved, PPC::VRSAVE); 277 278 // The SVR4 ABI reserves r2 and r13 279 if (Subtarget.isSVR4ABI()) { 280 // We only reserve r2 if we need to use the TOC pointer. If we have no 281 // explicit uses of the TOC pointer (meaning we're a leaf function with 282 // no constant-pool loads, etc.) and we have no potential uses inside an 283 // inline asm block, then we can treat r2 has an ordinary callee-saved 284 // register. 285 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 286 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 287 markSuperRegs(Reserved, PPC::R2); // System-reserved register 288 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register 289 } 290 291 // On PPC64, r13 is the thread pointer. Never allocate this register. 292 if (TM.isPPC64()) 293 markSuperRegs(Reserved, PPC::R13); 294 295 if (TFI->needsFP(MF)) 296 markSuperRegs(Reserved, PPC::R31); 297 298 bool IsPositionIndependent = TM.isPositionIndependent(); 299 if (hasBasePointer(MF)) { 300 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent) 301 markSuperRegs(Reserved, PPC::R29); 302 else 303 markSuperRegs(Reserved, PPC::R30); 304 } 305 306 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent) 307 markSuperRegs(Reserved, PPC::R30); 308 309 // Reserve Altivec registers when Altivec is unavailable. 310 if (!Subtarget.hasAltivec()) 311 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 312 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 313 markSuperRegs(Reserved, *I); 314 315 assert(checkAllSuperRegsMarked(Reserved)); 316 return Reserved; 317 } 318 319 bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg, 320 const MachineFunction &MF) const { 321 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 322 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 323 const MachineFrameInfo &MFI = MF.getFrameInfo(); 324 if (!TM.isPPC64()) 325 return false; 326 327 if (!Subtarget.isSVR4ABI()) 328 return false; 329 if (PhysReg == PPC::X2) 330 // X2 is guaranteed to be preserved within a function if it is reserved. 331 // The reason it's reserved is that it's the TOC pointer (and the function 332 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions 333 // with no TOC access), we can't claim that it is preserved. 334 return (getReservedRegs(MF).test(PPC::X2)); 335 if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects() 336 && !MFI.hasOpaqueSPAdjustment()) 337 // The value of the stack pointer does not change within a function after 338 // the prologue and before the epilogue if there are no dynamic allocations 339 // and no inline asm which clobbers X1. 340 return true; 341 return false; 342 } 343 344 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 345 MachineFunction &MF) const { 346 const PPCFrameLowering *TFI = getFrameLowering(MF); 347 const unsigned DefaultSafety = 1; 348 349 switch (RC->getID()) { 350 default: 351 return 0; 352 case PPC::G8RC_NOX0RegClassID: 353 case PPC::GPRC_NOR0RegClassID: 354 case PPC::SPERCRegClassID: 355 case PPC::SPE4RCRegClassID: 356 case PPC::G8RCRegClassID: 357 case PPC::GPRCRegClassID: { 358 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 359 return 32 - FP - DefaultSafety; 360 } 361 case PPC::F8RCRegClassID: 362 case PPC::F4RCRegClassID: 363 case PPC::QFRCRegClassID: 364 case PPC::QSRCRegClassID: 365 case PPC::QBRCRegClassID: 366 case PPC::VRRCRegClassID: 367 case PPC::VFRCRegClassID: 368 case PPC::VSLRCRegClassID: 369 return 32 - DefaultSafety; 370 case PPC::VSRCRegClassID: 371 case PPC::VSFRCRegClassID: 372 case PPC::VSSRCRegClassID: 373 return 64 - DefaultSafety; 374 case PPC::CRRCRegClassID: 375 return 8 - DefaultSafety; 376 } 377 } 378 379 const TargetRegisterClass * 380 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 381 const MachineFunction &MF) const { 382 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 383 if (Subtarget.hasVSX()) { 384 // With VSX, we can inflate various sub-register classes to the full VSX 385 // register set. 386 387 // For Power9 we allow the user to enable GPR to vector spills. 388 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add 389 // support to spill GPRC. 390 if (TM.isELFv2ABI()) { 391 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills && 392 RC == &PPC::G8RCRegClass) { 393 InflateGP8RC++; 394 return &PPC::SPILLTOVSRRCRegClass; 395 } 396 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills) 397 InflateGPRC++; 398 } 399 if (RC == &PPC::F8RCRegClass) 400 return &PPC::VSFRCRegClass; 401 else if (RC == &PPC::VRRCRegClass) 402 return &PPC::VSRCRegClass; 403 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector()) 404 return &PPC::VSSRCRegClass; 405 } 406 407 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 408 } 409 410 //===----------------------------------------------------------------------===// 411 // Stack Frame Processing methods 412 //===----------------------------------------------------------------------===// 413 414 /// lowerDynamicAlloc - Generate the code for allocating an object in the 415 /// current frame. The sequence of code will be in the general form 416 /// 417 /// addi R0, SP, \#frameSize ; get the address of the previous frame 418 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 419 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 420 /// 421 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 422 // Get the instruction. 423 MachineInstr &MI = *II; 424 // Get the instruction's basic block. 425 MachineBasicBlock &MBB = *MI.getParent(); 426 // Get the basic block's function. 427 MachineFunction &MF = *MBB.getParent(); 428 // Get the frame info. 429 MachineFrameInfo &MFI = MF.getFrameInfo(); 430 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 431 // Get the instruction info. 432 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 433 // Determine whether 64-bit pointers are used. 434 bool LP64 = TM.isPPC64(); 435 DebugLoc dl = MI.getDebugLoc(); 436 437 // Get the maximum call stack size. 438 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); 439 // Get the total frame size. 440 unsigned FrameSize = MFI.getStackSize(); 441 442 // Get stack alignments. 443 const PPCFrameLowering *TFI = getFrameLowering(MF); 444 unsigned TargetAlign = TFI->getStackAlignment(); 445 unsigned MaxAlign = MFI.getMaxAlignment(); 446 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 447 "Maximum call-frame size not sufficiently aligned"); 448 449 // Determine the previous frame's address. If FrameSize can't be 450 // represented as 16 bits or we need special alignment, then we load the 451 // previous frame's address from 0(SP). Why not do an addis of the hi? 452 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 453 // Constructing the constant and adding would take 3 instructions. 454 // Fortunately, a frame greater than 32K is rare. 455 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 456 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 457 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 458 459 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 460 if (LP64) 461 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg) 462 .addReg(PPC::X31) 463 .addImm(FrameSize); 464 else 465 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 466 .addReg(PPC::R31) 467 .addImm(FrameSize); 468 } else if (LP64) { 469 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 470 .addImm(0) 471 .addReg(PPC::X1); 472 } else { 473 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 474 .addImm(0) 475 .addReg(PPC::R1); 476 } 477 478 bool KillNegSizeReg = MI.getOperand(1).isKill(); 479 unsigned NegSizeReg = MI.getOperand(1).getReg(); 480 481 // Grow the stack and update the stack pointer link, then determine the 482 // address of new allocated space. 483 if (LP64) { 484 if (MaxAlign > TargetAlign) { 485 unsigned UnalNegSizeReg = NegSizeReg; 486 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 487 488 // Unfortunately, there is no andi, only andi., and we can't insert that 489 // here because we might clobber cr0 while it is live. 490 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 491 .addImm(~(MaxAlign-1)); 492 493 unsigned NegSizeReg1 = NegSizeReg; 494 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 495 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 496 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 497 .addReg(NegSizeReg1, RegState::Kill); 498 KillNegSizeReg = true; 499 } 500 501 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 502 .addReg(Reg, RegState::Kill) 503 .addReg(PPC::X1) 504 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 505 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 506 .addReg(PPC::X1) 507 .addImm(maxCallFrameSize); 508 } else { 509 if (MaxAlign > TargetAlign) { 510 unsigned UnalNegSizeReg = NegSizeReg; 511 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 512 513 // Unfortunately, there is no andi, only andi., and we can't insert that 514 // here because we might clobber cr0 while it is live. 515 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 516 .addImm(~(MaxAlign-1)); 517 518 unsigned NegSizeReg1 = NegSizeReg; 519 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 520 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 521 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 522 .addReg(NegSizeReg1, RegState::Kill); 523 KillNegSizeReg = true; 524 } 525 526 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 527 .addReg(Reg, RegState::Kill) 528 .addReg(PPC::R1) 529 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 530 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 531 .addReg(PPC::R1) 532 .addImm(maxCallFrameSize); 533 } 534 535 // Discard the DYNALLOC instruction. 536 MBB.erase(II); 537 } 538 539 void PPCRegisterInfo::lowerDynamicAreaOffset( 540 MachineBasicBlock::iterator II) const { 541 // Get the instruction. 542 MachineInstr &MI = *II; 543 // Get the instruction's basic block. 544 MachineBasicBlock &MBB = *MI.getParent(); 545 // Get the basic block's function. 546 MachineFunction &MF = *MBB.getParent(); 547 // Get the frame info. 548 MachineFrameInfo &MFI = MF.getFrameInfo(); 549 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 550 // Get the instruction info. 551 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 552 553 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize(); 554 bool is64Bit = TM.isPPC64(); 555 DebugLoc dl = MI.getDebugLoc(); 556 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), 557 MI.getOperand(0).getReg()) 558 .addImm(maxCallFrameSize); 559 MBB.erase(II); 560 } 561 562 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 563 /// reserving a whole register (R0), we scrounge for one here. This generates 564 /// code like this: 565 /// 566 /// mfcr rA ; Move the conditional register into GPR rA. 567 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 568 /// stw rA, FI ; Store rA to the frame. 569 /// 570 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 571 unsigned FrameIndex) const { 572 // Get the instruction. 573 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 574 // Get the instruction's basic block. 575 MachineBasicBlock &MBB = *MI.getParent(); 576 MachineFunction &MF = *MBB.getParent(); 577 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 578 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 579 DebugLoc dl = MI.getDebugLoc(); 580 581 bool LP64 = TM.isPPC64(); 582 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 583 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 584 585 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 586 unsigned SrcReg = MI.getOperand(0).getReg(); 587 588 // We need to store the CR in the low 4-bits of the saved value. First, issue 589 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 590 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 591 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 592 593 // If the saved register wasn't CR0, shift the bits left so that they are in 594 // CR0's slot. 595 if (SrcReg != PPC::CR0) { 596 unsigned Reg1 = Reg; 597 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 598 599 // rlwinm rA, rA, ShiftBits, 0, 31. 600 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 601 .addReg(Reg1, RegState::Kill) 602 .addImm(getEncodingValue(SrcReg) * 4) 603 .addImm(0) 604 .addImm(31); 605 } 606 607 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 608 .addReg(Reg, RegState::Kill), 609 FrameIndex); 610 611 // Discard the pseudo instruction. 612 MBB.erase(II); 613 } 614 615 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 616 unsigned FrameIndex) const { 617 // Get the instruction. 618 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 619 // Get the instruction's basic block. 620 MachineBasicBlock &MBB = *MI.getParent(); 621 MachineFunction &MF = *MBB.getParent(); 622 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 623 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 624 DebugLoc dl = MI.getDebugLoc(); 625 626 bool LP64 = TM.isPPC64(); 627 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 628 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 629 630 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 631 unsigned DestReg = MI.getOperand(0).getReg(); 632 assert(MI.definesRegister(DestReg) && 633 "RESTORE_CR does not define its destination"); 634 635 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 636 Reg), FrameIndex); 637 638 // If the reloaded register isn't CR0, shift the bits right so that they are 639 // in the right CR's slot. 640 if (DestReg != PPC::CR0) { 641 unsigned Reg1 = Reg; 642 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 643 644 unsigned ShiftBits = getEncodingValue(DestReg)*4; 645 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 646 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 647 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 648 .addImm(31); 649 } 650 651 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 652 .addReg(Reg, RegState::Kill); 653 654 // Discard the pseudo instruction. 655 MBB.erase(II); 656 } 657 658 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 659 unsigned FrameIndex) const { 660 // Get the instruction. 661 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 662 // Get the instruction's basic block. 663 MachineBasicBlock &MBB = *MI.getParent(); 664 MachineFunction &MF = *MBB.getParent(); 665 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 666 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 667 DebugLoc dl = MI.getDebugLoc(); 668 669 bool LP64 = TM.isPPC64(); 670 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 671 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 672 673 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 674 unsigned SrcReg = MI.getOperand(0).getReg(); 675 676 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 677 getCRFromCRBit(SrcReg)) 678 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 679 680 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 681 .addReg(getCRFromCRBit(SrcReg)); 682 683 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 684 // store is the first one. Mask all but that bit. 685 unsigned Reg1 = Reg; 686 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 687 688 // rlwinm rA, rA, ShiftBits, 0, 0. 689 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 690 .addReg(Reg1, RegState::Kill) 691 .addImm(getEncodingValue(SrcReg)) 692 .addImm(0).addImm(0); 693 694 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 695 .addReg(Reg, RegState::Kill), 696 FrameIndex); 697 698 // Discard the pseudo instruction. 699 MBB.erase(II); 700 } 701 702 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 703 unsigned FrameIndex) const { 704 // Get the instruction. 705 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 706 // Get the instruction's basic block. 707 MachineBasicBlock &MBB = *MI.getParent(); 708 MachineFunction &MF = *MBB.getParent(); 709 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 710 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 711 DebugLoc dl = MI.getDebugLoc(); 712 713 bool LP64 = TM.isPPC64(); 714 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 715 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 716 717 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 718 unsigned DestReg = MI.getOperand(0).getReg(); 719 assert(MI.definesRegister(DestReg) && 720 "RESTORE_CRBIT does not define its destination"); 721 722 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 723 Reg), FrameIndex); 724 725 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 726 727 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 728 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 729 .addReg(getCRFromCRBit(DestReg)); 730 731 unsigned ShiftBits = getEncodingValue(DestReg); 732 // rlwimi r11, r10, 32-ShiftBits, ..., ... 733 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 734 .addReg(RegO, RegState::Kill) 735 .addReg(Reg, RegState::Kill) 736 .addImm(ShiftBits ? 32 - ShiftBits : 0) 737 .addImm(ShiftBits) 738 .addImm(ShiftBits); 739 740 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 741 getCRFromCRBit(DestReg)) 742 .addReg(RegO, RegState::Kill) 743 // Make sure we have a use dependency all the way through this 744 // sequence of instructions. We can't have the other bits in the CR 745 // modified in between the mfocrf and the mtocrf. 746 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 747 748 // Discard the pseudo instruction. 749 MBB.erase(II); 750 } 751 752 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 753 unsigned FrameIndex) const { 754 // Get the instruction. 755 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 756 // Get the instruction's basic block. 757 MachineBasicBlock &MBB = *MI.getParent(); 758 MachineFunction &MF = *MBB.getParent(); 759 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 760 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 761 DebugLoc dl = MI.getDebugLoc(); 762 763 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 764 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 765 unsigned SrcReg = MI.getOperand(0).getReg(); 766 767 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 768 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 769 770 addFrameReference( 771 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill), 772 FrameIndex); 773 774 // Discard the pseudo instruction. 775 MBB.erase(II); 776 } 777 778 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 779 unsigned FrameIndex) const { 780 // Get the instruction. 781 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 782 // Get the instruction's basic block. 783 MachineBasicBlock &MBB = *MI.getParent(); 784 MachineFunction &MF = *MBB.getParent(); 785 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 786 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 787 DebugLoc dl = MI.getDebugLoc(); 788 789 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 790 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 791 unsigned DestReg = MI.getOperand(0).getReg(); 792 assert(MI.definesRegister(DestReg) && 793 "RESTORE_VRSAVE does not define its destination"); 794 795 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 796 Reg), FrameIndex); 797 798 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 799 .addReg(Reg, RegState::Kill); 800 801 // Discard the pseudo instruction. 802 MBB.erase(II); 803 } 804 805 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 806 unsigned Reg, int &FrameIdx) const { 807 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 808 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 809 // ABI, return true to prevent allocating an additional frame slot. 810 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 811 // is arbitrary and will be subsequently ignored. For 32-bit, we have 812 // previously created the stack slot if needed, so return its FrameIdx. 813 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 814 if (TM.isPPC64()) 815 FrameIdx = 0; 816 else { 817 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 818 FrameIdx = FI->getCRSpillFrameIndex(); 819 } 820 return true; 821 } 822 return false; 823 } 824 825 // If the offset must be a multiple of some value, return what that value is. 826 static unsigned offsetMinAlign(const MachineInstr &MI) { 827 unsigned OpC = MI.getOpcode(); 828 829 switch (OpC) { 830 default: 831 return 1; 832 case PPC::LWA: 833 case PPC::LWA_32: 834 case PPC::LD: 835 case PPC::LDU: 836 case PPC::STD: 837 case PPC::STDU: 838 case PPC::DFLOADf32: 839 case PPC::DFLOADf64: 840 case PPC::DFSTOREf32: 841 case PPC::DFSTOREf64: 842 case PPC::LXSD: 843 case PPC::LXSSP: 844 case PPC::STXSD: 845 case PPC::STXSSP: 846 return 4; 847 case PPC::LXV: 848 case PPC::STXV: 849 return 16; 850 } 851 } 852 853 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 854 static unsigned getOffsetONFromFION(const MachineInstr &MI, 855 unsigned FIOperandNum) { 856 // Take into account whether it's an add or mem instruction 857 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 858 if (MI.isInlineAsm()) 859 OffsetOperandNo = FIOperandNum - 1; 860 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 861 MI.getOpcode() == TargetOpcode::PATCHPOINT) 862 OffsetOperandNo = FIOperandNum + 1; 863 864 return OffsetOperandNo; 865 } 866 867 void 868 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 869 int SPAdj, unsigned FIOperandNum, 870 RegScavenger *RS) const { 871 assert(SPAdj == 0 && "Unexpected"); 872 873 // Get the instruction. 874 MachineInstr &MI = *II; 875 // Get the instruction's basic block. 876 MachineBasicBlock &MBB = *MI.getParent(); 877 // Get the basic block's function. 878 MachineFunction &MF = *MBB.getParent(); 879 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 880 // Get the instruction info. 881 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 882 // Get the frame info. 883 MachineFrameInfo &MFI = MF.getFrameInfo(); 884 DebugLoc dl = MI.getDebugLoc(); 885 886 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 887 888 // Get the frame index. 889 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 890 891 // Get the frame pointer save index. Users of this index are primarily 892 // DYNALLOC instructions. 893 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 894 int FPSI = FI->getFramePointerSaveIndex(); 895 // Get the instruction opcode. 896 unsigned OpC = MI.getOpcode(); 897 898 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { 899 lowerDynamicAreaOffset(II); 900 return; 901 } 902 903 // Special case for dynamic alloca. 904 if (FPSI && FrameIndex == FPSI && 905 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 906 lowerDynamicAlloc(II); 907 return; 908 } 909 910 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 911 if (OpC == PPC::SPILL_CR) { 912 lowerCRSpilling(II, FrameIndex); 913 return; 914 } else if (OpC == PPC::RESTORE_CR) { 915 lowerCRRestore(II, FrameIndex); 916 return; 917 } else if (OpC == PPC::SPILL_CRBIT) { 918 lowerCRBitSpilling(II, FrameIndex); 919 return; 920 } else if (OpC == PPC::RESTORE_CRBIT) { 921 lowerCRBitRestore(II, FrameIndex); 922 return; 923 } else if (OpC == PPC::SPILL_VRSAVE) { 924 lowerVRSAVESpilling(II, FrameIndex); 925 return; 926 } else if (OpC == PPC::RESTORE_VRSAVE) { 927 lowerVRSAVERestore(II, FrameIndex); 928 return; 929 } 930 931 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 932 MI.getOperand(FIOperandNum).ChangeToRegister( 933 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 934 935 // If the instruction is not present in ImmToIdxMap, then it has no immediate 936 // form (and must be r+r). 937 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 938 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 939 940 // Now add the frame object offset to the offset from r1. 941 int Offset = MFI.getObjectOffset(FrameIndex); 942 Offset += MI.getOperand(OffsetOperandNo).getImm(); 943 944 // If we're not using a Frame Pointer that has been set to the value of the 945 // SP before having the stack size subtracted from it, then add the stack size 946 // to Offset to get the correct offset. 947 // Naked functions have stack size 0, although getStackSize may not reflect 948 // that because we didn't call all the pieces that compute it for naked 949 // functions. 950 if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) { 951 if (!(hasBasePointer(MF) && FrameIndex < 0)) 952 Offset += MFI.getStackSize(); 953 } 954 955 // If we can, encode the offset directly into the instruction. If this is a 956 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 957 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 958 // clear can be encoded. This is extremely uncommon, because normally you 959 // only "std" to a stack slot that is at least 4-byte aligned, but it can 960 // happen in invalid code. 961 assert(OpC != PPC::DBG_VALUE && 962 "This should be handled in a target-independent way"); 963 if (!noImmForm && ((isInt<16>(Offset) && 964 ((Offset % offsetMinAlign(MI)) == 0)) || 965 OpC == TargetOpcode::STACKMAP || 966 OpC == TargetOpcode::PATCHPOINT)) { 967 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 968 return; 969 } 970 971 // The offset doesn't fit into a single register, scavenge one to build the 972 // offset in. 973 974 bool is64Bit = TM.isPPC64(); 975 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 976 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 977 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 978 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 979 SReg = MF.getRegInfo().createVirtualRegister(RC); 980 981 // Insert a set of rA with the full offset value before the ld, st, or add 982 if (isInt<16>(Offset)) 983 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg) 984 .addImm(Offset); 985 else { 986 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 987 .addImm(Offset >> 16); 988 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 989 .addReg(SRegHi, RegState::Kill) 990 .addImm(Offset); 991 } 992 993 // Convert into indexed form of the instruction: 994 // 995 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 996 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 997 unsigned OperandBase; 998 999 if (noImmForm) 1000 OperandBase = 1; 1001 else if (OpC != TargetOpcode::INLINEASM) { 1002 assert(ImmToIdxMap.count(OpC) && 1003 "No indexed form of load or store available!"); 1004 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 1005 MI.setDesc(TII.get(NewOpcode)); 1006 OperandBase = 1; 1007 } else { 1008 OperandBase = OffsetOperandNo; 1009 } 1010 1011 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 1012 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 1013 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 1014 } 1015 1016 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1017 const PPCFrameLowering *TFI = getFrameLowering(MF); 1018 1019 if (!TM.isPPC64()) 1020 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 1021 else 1022 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 1023 } 1024 1025 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 1026 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1027 if (!hasBasePointer(MF)) 1028 return getFrameRegister(MF); 1029 1030 if (TM.isPPC64()) 1031 return PPC::X30; 1032 1033 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent()) 1034 return PPC::R29; 1035 1036 return PPC::R30; 1037 } 1038 1039 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 1040 if (!EnableBasePointer) 1041 return false; 1042 if (AlwaysBasePointer) 1043 return true; 1044 1045 // If we need to realign the stack, then the stack pointer can no longer 1046 // serve as an offset into the caller's stack space. As a result, we need a 1047 // base pointer. 1048 return needsStackRealignment(MF); 1049 } 1050 1051 /// Returns true if the instruction's frame index 1052 /// reference would be better served by a base register other than FP 1053 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 1054 /// references it should create new base registers for. 1055 bool PPCRegisterInfo:: 1056 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 1057 assert(Offset < 0 && "Local offset must be negative"); 1058 1059 // It's the load/store FI references that cause issues, as it can be difficult 1060 // to materialize the offset if it won't fit in the literal field. Estimate 1061 // based on the size of the local frame and some conservative assumptions 1062 // about the rest of the stack frame (note, this is pre-regalloc, so 1063 // we don't know everything for certain yet) whether this offset is likely 1064 // to be out of range of the immediate. Return true if so. 1065 1066 // We only generate virtual base registers for loads and stores that have 1067 // an r+i form. Return false for everything else. 1068 unsigned OpC = MI->getOpcode(); 1069 if (!ImmToIdxMap.count(OpC)) 1070 return false; 1071 1072 // Don't generate a new virtual base register just to add zero to it. 1073 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 1074 MI->getOperand(2).getImm() == 0) 1075 return false; 1076 1077 MachineBasicBlock &MBB = *MI->getParent(); 1078 MachineFunction &MF = *MBB.getParent(); 1079 const PPCFrameLowering *TFI = getFrameLowering(MF); 1080 unsigned StackEst = TFI->determineFrameLayout(MF, false, true); 1081 1082 // If we likely don't need a stack frame, then we probably don't need a 1083 // virtual base register either. 1084 if (!StackEst) 1085 return false; 1086 1087 // Estimate an offset from the stack pointer. 1088 // The incoming offset is relating to the SP at the start of the function, 1089 // but when we access the local it'll be relative to the SP after local 1090 // allocation, so adjust our SP-relative offset by that allocation size. 1091 Offset += StackEst; 1092 1093 // The frame pointer will point to the end of the stack, so estimate the 1094 // offset as the difference between the object offset and the FP location. 1095 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); 1096 } 1097 1098 /// Insert defining instruction(s) for BaseReg to 1099 /// be a pointer to FrameIdx at the beginning of the basic block. 1100 void PPCRegisterInfo:: 1101 materializeFrameBaseRegister(MachineBasicBlock *MBB, 1102 unsigned BaseReg, int FrameIdx, 1103 int64_t Offset) const { 1104 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 1105 1106 MachineBasicBlock::iterator Ins = MBB->begin(); 1107 DebugLoc DL; // Defaults to "unknown" 1108 if (Ins != MBB->end()) 1109 DL = Ins->getDebugLoc(); 1110 1111 const MachineFunction &MF = *MBB->getParent(); 1112 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1113 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1114 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1115 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1116 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1117 1118 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1119 .addFrameIndex(FrameIdx).addImm(Offset); 1120 } 1121 1122 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1123 int64_t Offset) const { 1124 unsigned FIOperandNum = 0; 1125 while (!MI.getOperand(FIOperandNum).isFI()) { 1126 ++FIOperandNum; 1127 assert(FIOperandNum < MI.getNumOperands() && 1128 "Instr doesn't have FrameIndex operand!"); 1129 } 1130 1131 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1132 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1133 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1134 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1135 1136 MachineBasicBlock &MBB = *MI.getParent(); 1137 MachineFunction &MF = *MBB.getParent(); 1138 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1139 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1140 const MCInstrDesc &MCID = MI.getDesc(); 1141 MachineRegisterInfo &MRI = MF.getRegInfo(); 1142 MRI.constrainRegClass(BaseReg, 1143 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1144 } 1145 1146 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1147 unsigned BaseReg, 1148 int64_t Offset) const { 1149 unsigned FIOperandNum = 0; 1150 while (!MI->getOperand(FIOperandNum).isFI()) { 1151 ++FIOperandNum; 1152 assert(FIOperandNum < MI->getNumOperands() && 1153 "Instr doesn't have FrameIndex operand!"); 1154 } 1155 1156 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1157 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1158 1159 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1160 MI->getOpcode() == TargetOpcode::STACKMAP || 1161 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1162 (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0); 1163 } 1164
