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    Searched defs:mxc_ccm (Results 1 - 25 of 30) sorted by null

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  /external/u-boot/board/engicam/imx6ul/
imx6ul.c 51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
56 clrbits_le32(&mxc_ccm->CCGR4,
68 clrbits_le32(&mxc_ccm->cscmr1,
71 clrsetbits_le32(&mxc_ccm->cscdr1,
78 setbits_le32(&mxc_ccm->CCGR4,
86 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/ge/mx53ppd/
mx53ppd_video.c 79 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
83 clrsetbits_le32(&mxc_ccm->cscmr2,
89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
  /external/u-boot/board/engicam/imx6q/
imx6q.c 50 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
56 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 clrsetbits_le32(&mxc_ccm->cs2cdr,
68 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
71 setbits_le32(&mxc_ccm->CCGR4,
79 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
143 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
150 reg = __raw_readl(&mxc_ccm->CCGR3);
152 writel(reg, &mxc_ccm->CCGR3);
155 reg = readl(&mxc_ccm->cs2cdr)
    [all...]
  /external/u-boot/board/aristainetos/
aristainetos-v1.c 221 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
226 reg = readl(&mxc_ccm->cs2cdr);
230 writel(reg, &mxc_ccm->cs2cdr);
aristainetos.c 232 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
239 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
242 clrsetbits_le32(&mxc_ccm->cs2cdr,
251 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
254 setbits_le32(&mxc_ccm->CCGR4,
262 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/barco/platinum/
platinum.c 65 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
71 clrsetbits_le32(&mxc_ccm->cs2cdr,
80 setbits_le32(&mxc_ccm->CCGR4,
88 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/barco/titanium/
titanium.c 158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
165 clrsetbits_le32(&mxc_ccm->cs2cdr,
174 setbits_le32(&mxc_ccm->CCGR4,
182 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/compulab/cm_fx6/
spl.c 313 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
320 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
cm_fx6.c 80 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
82 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  /external/u-boot/board/freescale/mx51evk/
mx51evk.c 173 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; local
215 writel(0x0, &mxc_ccm->cacrr);
  /external/u-boot/board/k+p/kp_imx6q_tpc/
kp_imx6q_tpc.c 262 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
268 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  /external/u-boot/board/dhelectronics/dh_imx6/
dh_imx6.c 334 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
340 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  /external/u-boot/board/embest/mx6boards/
mx6boards.c 461 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
469 setbits_le32(&mxc_ccm->CCGR3,
473 clrsetbits_le32(&mxc_ccm->cs2cdr,
477 setbits_le32(&mxc_ccm->cscmr2,
480 setbits_le32(&mxc_ccm->chsccdr,
  /external/u-boot/board/freescale/mx6sxsabreauto/
mx6sxsabreauto.c 275 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
285 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/kosagi/novena/
video.c 386 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
394 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
397 clrsetbits_le32(&mxc_ccm->cs2cdr,
402 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
405 clrsetbits_le32(&mxc_ccm->chsccdr,
  /external/u-boot/board/phytec/pcm058/
pcm058.c 292 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
298 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
301 clrsetbits_le32(&mxc_ccm->cs2cdr,
310 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
313 setbits_le32(&mxc_ccm->CCGR4,
321 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/board/wandboard/
wandboard.c 408 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
414 reg = readl(&mxc_ccm->chsccdr);
417 writel(reg, &mxc_ccm->chsccdr);
  /external/u-boot/arch/arm/mach-imx/mx6/
soc.c 300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
304 reg = readl(&mxc_ccm->cbcdr);
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
312 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
314 reg = readl(&mxc_ccm->ccdr);
321 writel(reg, &mxc_ccm->ccdr);
619 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
625 reg = readl(&mxc_ccm->CCGR2);
628 writel(reg, &mxc_ccm->CCGR2);
630 reg = readl(&mxc_ccm->chsccdr)
    [all...]
clock.c 1317 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
1334 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
1359 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
1380 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
    [all...]
  /external/u-boot/board/advantech/dms-ba16/
dms-ba16.c 397 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
400 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
405 clrsetbits_le32(&mxc_ccm->chsccdr,
411 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  /external/u-boot/board/freescale/mx6sabreauto/
mx6sabreauto.c 365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
375 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
510 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
519 reg = readl(&mxc_ccm->CCGR3);
521 writel(reg, &mxc_ccm->CCGR3);
524 reg = readl(&mxc_ccm->cs2cdr);
529 writel(reg, &mxc_ccm->cs2cdr);
531 reg = readl(&mxc_ccm->cscmr2);
533 writel(reg, &mxc_ccm->cscmr2);
535 reg = readl(&mxc_ccm->chsccdr)
    [all...]
  /external/u-boot/board/freescale/mx6sabresd/
mx6sabresd.c 490 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
501 reg = readl(&mxc_ccm->CCGR3);
503 writel(reg, &mxc_ccm->CCGR3);
506 reg = readl(&mxc_ccm->cs2cdr);
511 writel(reg, &mxc_ccm->cs2cdr);
513 reg = readl(&mxc_ccm->cscmr2);
515 writel(reg, &mxc_ccm->cscmr2);
517 reg = readl(&mxc_ccm->chsccdr);
522 writel(reg, &mxc_ccm->chsccdr);
  /external/u-boot/board/phytec/pfla02/
pfla02.c 274 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
280 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
283 clrsetbits_le32(&mxc_ccm->cs2cdr,
292 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
295 setbits_le32(&mxc_ccm->CCGR4,
303 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  /external/u-boot/arch/arm/mach-imx/mx5/
clock.c 73 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; variable in typeref:struct:mxc_ccm_reg
77 clrsetbits_le32(&mxc_ccm->cscmr1,
80 clrsetbits_le32(&mxc_ccm->cscdr1,
91 clrsetbits_le32(&mxc_ccm->CCGR2,
111 setbits_le32(&mxc_ccm->CCGR1, mask);
113 clrbits_le32(&mxc_ccm->CCGR1, mask);
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
128 clrsetbits_le32(&mxc_ccm->CCGR2,
142 clrsetbits_le32(&mxc_ccm->CCGR4,
151 clrsetbits_le32(&mxc_ccm->CCGR4
    [all...]
  /external/u-boot/board/boundary/nitrogen6x/
nitrogen6x.c 756 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local
763 reg = __raw_readl(&mxc_ccm->CCGR3);
765 writel(reg, &mxc_ccm->CCGR3);
768 reg = readl(&mxc_ccm->cs2cdr);
773 writel(reg, &mxc_ccm->cs2cdr);
775 reg = readl(&mxc_ccm->cscmr2);
777 writel(reg, &mxc_ccm->cscmr2);
779 reg = readl(&mxc_ccm->chsccdr);
782 writel(reg, &mxc_ccm->chsccdr);

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