| /external/u-boot/drivers/pci/ |
| pcie_ecam_generic.c | 3 * Generic PCIE host provided by e.g. QEMU
17 * struct generic_ecam_pcie - generic_ecam PCIe controller state
27 * @bdf: Identifies the PCIe device to access
31 * Calculates the address that should be accessed to perform a PCIe
32 * configuration space access for a given device identified by the PCIe
33 * controller device @pcie and the bus, device & function numbers in @bdf. If
41 struct generic_ecam_pcie *pcie = dev_get_priv(bus); local
44 addr = pcie->cfg_base;
57 * @bdf: Identifies the PCIe device to access
77 * @bdf: Identifies the PCIe device to acces
106 struct generic_ecam_pcie *pcie = dev_get_priv(dev); local
[all...] |
| pcie_xilinx.c | 15 * struct xilinx_pcie - Xilinx PCIe controller state
27 * pcie_xilinx_link_up() - Check whether the PCIe link is up
28 * @pcie: Pointer to the PCI controller state
30 * Checks whether the PCIe link for the given device is up or down.
34 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
44 * @bdf: Identifies the PCIe device to access
48 * Calculates the address that should be accessed to perform a PCIe
49 * configuration space access for a given device identified by the PCIe
50 * controller device @pcie and the bus, device & function numbers in @bdf. I
60 struct xilinx_pcie *pcie = dev_get_priv(udev); local
142 struct xilinx_pcie *pcie = dev_get_priv(dev); local
[all...] |
| pcie_layerscape_fixup.c | 5 * Layerscape PCIe driver
25 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
28 return pcie->next_lut_index++;
33 /* returns the next available streamid for pcie, -errno if failed */
44 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
47 if (pcie->big_endian)
48 out_be32(pcie->lut + offset, value);
50 out_le32(pcie->lut + offset, value);
56 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid
181 struct ls_pcie *pcie; local
255 struct ls_pcie *pcie; local
[all...] |
| pcie_layerscape.c | 5 * Layerscape PCIe driver
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
27 return in_le32(pcie->dbi + offset);
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
33 out_le32(pcie->dbi + offset, value);
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
38 if (pcie->big_endian)
39 return in_be32(pcie->ctrl + offset);
41 return in_le32(pcie->ctrl + offset);
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value
246 struct ls_pcie *pcie = dev_get_priv(bus); local
438 struct ls_pcie *pcie = dev_get_priv(dev); local
[all...] |
| fsl_pci_init.c | 13 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
382 /* see if we are a PCIe or PCI controller */
391 /* boot from PCIE --master */
393 char pcie[6]; local
394 sprintf(pcie, "PCIE%d", pci_info->pci_num);
396 if (s && (strcmp(s, pcie) == 0)) {
397 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
425 * - ICCA (PCIe)
448 /* assert PCIe reset *
676 char pcie[6]; local
[all...] |
| pcie_intel_fpga.c | 3 * Intel FPGA PCIe host controller driver
37 #define RP_CFG_ADDR(pcie, reg) \
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf)
228 struct intel_fpga_pcie *pcie = dev_get_priv(bus); local
248 struct intel_fpga_pcie *pcie = dev_get_priv(bus); local
329 struct intel_fpga_pcie *pcie = dev_get_priv(bus); local
351 struct intel_fpga_pcie *pcie = dev_get_priv(bus); local
365 struct intel_fpga_pcie *pcie = dev_get_priv(dev); local
380 struct intel_fpga_pcie *pcie = dev_get_priv(dev); local
[all...] |
| pci_mvebu.c | 3 * PCIe driver for Marvell MVEBU SoCs
22 /* PCIe unit register offsets */
83 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
106 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
114 pcie->port = port[pex_idx];
115 pcie->lane = lane[pex_idx];
141 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
151 pcie->port = port[pex_idx];
152 pcie->lane = lane[pex_idx];
166 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
217 struct mvebu_pcie *pcie = hose_to_pcie(hose); local
252 struct mvebu_pcie *pcie = hose_to_pcie(hose); local
347 struct mvebu_pcie *pcie = &pcie_bus[i]; local
[all...] |
| pcie_dw_mvebu.c | 97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
134 * @pcie: Pointer to the PCI controller state
138 * @pci_addr: the pcie bus address for the translation entry
141 static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
146 pcie->ctrl_base + PCIE_ATU_VIEWPORT);
147 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
148 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE)
247 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); local
293 struct pcie_dw_mvebu *pcie = dev_get_priv(bus); local
476 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); local
546 struct pcie_dw_mvebu *pcie = dev_get_priv(dev); local
[all...] |
| pci-aardvark.c | 34 /* PCIe core registers */
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
135 * struct pcie_advk - Advk PCIe controller state
138 * @first_busno: This driver supports multiple PCIe controllers.
139 * first_busno stores the bus number of the PCIe root-port
140 * number which may vary depending on the PCIe setup
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
152 writel(val, pcie->base + reg);
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg
304 struct pcie_advk *pcie = dev_get_priv(bus); local
401 struct pcie_advk *pcie = dev_get_priv(bus); local
611 struct pcie_advk *pcie = dev_get_priv(dev); local
660 struct pcie_advk *pcie = dev_get_priv(dev); local
[all...] |
| pci_tegra.c | 6 * Based on NVIDIA PCIe driver
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
164 * entries, one entry per PCIe port. These field definitions and desired
195 struct tegra_pcie *pcie; member in struct:tegra_pcie_port
240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
243 writel(value, pcie->afi.start + offset);
246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
248 return readl(pcie->afi.start + offset);
251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
254 writel(value, pcie->pads.start + offset)
315 struct tegra_pcie *pcie = dev_get_priv(bus); local
347 struct tegra_pcie *pcie = dev_get_priv(bus); local
802 struct tegra_pcie *pcie = dev_get_priv(bus); local
921 struct tegra_pcie *pcie = port->pcie; local
1095 struct tegra_pcie *pcie = dev_get_priv(dev); local
1111 struct tegra_pcie *pcie = dev_get_priv(dev); local
[all...] |
| /external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| immap_lsch2.h | 617 } pcie[3]; member in struct:ccsr_serdes
|
