| /external/u-boot/drivers/ddr/marvell/axp/ |
| ddr3_read_leveling.c | 91 u32 delay, phase, pup, cs; local
99 for (pup = 0;
100 pup < dram_info->num_of_total_pups;
101 pup++) {
102 if (pup == dram_info->num_of_std_pups
104 pup = ECC_PUP;
107 pup);
111 dram_info->rl_val[cs][pup][P] = phase;
116 dram_info->rl_val[cs][pup][D] = delay;
117 dram_info->rl_val[cs][pup][S]
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; local
403 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, local
755 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, local
[all...] |
| ddr3_hw_training.c | 545 * Perform DDR3 PUP Indirect Write
547 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay)
551 if (pup == PUP_BC)
554 reg |= (pup << REG_PHY_PUP_OFFS);
575 if (pup == PUP_BC)
578 reg |= (pup << REG_PHY_PUP_OFFS);
595 * Perform DDR3 PUP Indirect Read
597 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup)
601 reg = (pup << REG_PHY_PUP_OFFS) |
623 /* Enable SW override - Required for the ECC Pup */
697 u32 val, pup, tmp_cs, cs, i, dq; local
1048 u32 pup, reg, phase; local
[all...] |
| ddr3_pbs.c | 44 /* PBS locked dq (per pup) */
66 static void ddr3_pbs_write_pup_dqs_reg(u32 cs, u32 pup, u32 dqs_delay);
96 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; local
124 for (pup = 0; pup < pups; pup++) {
126 skew_sum_array[pup][dq] = 0;
138 * This parameter stores the current PUP
145 /* Only 1 pup in this case */
172 for (pup = 0; pup < cur_max_pup; pup++)
411 u32 cur_max_pup, pup; local
538 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; local
923 u32 cur_max_pup, pup, pass_pup; local
1148 u32 pup, dq; local
1418 u32 pup, phys_pup, dq; local
[all...] |
| ddr3_sdram.c | 27 /* PBS locked dq (per pup) */
91 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
100 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
107 *pup |= (1 << (uk + (PUP_NUM_32BIT *
129 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
136 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
143 *pup |= (1 << (uk % PUP_NUM_16BIT));
150 * Desc: Execute compare per PUP
206 * Desc: Execute compare per PUP
225 u32 pup = 0 local
291 u32 ui, dq, pup; local
[all...] |
| ddr3_write_leveling.c | 49 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
66 u32 reg, phase, delay, cs, pup; local
108 for (pup = 0;
109 pup < dram_info->num_of_total_pups;
110 pup++) {
111 if (pup == dram_info->num_of_std_pups
113 pup = ECC_PUP;
116 pup);
121 dram_info->wl_val[cs][pup][P] = phase;
122 dram_info->wl_val[cs][pup][D] = delay
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; local
474 u32 reg, phase, delay, cs, pup, pup_num; local
659 u32 reg, cs, cnt, pup, max_pup_num; local
884 u32 reg, cs, cnt, pup; local
1127 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, local
[all...] |
| ddr3_dqs.c | 68 int ddr3_check_window_limits(u32 pup, int high_limit, int low_limit, int is_tx,
297 u32 victim_dq, pup, tmp; local
299 u32 max_pup; /* maximal pup index */
316 int pup_adll_limit_state[MAX_PUP_NUM]; /* hold state of each pup */
326 for (pup = 0; pup < max_pup; pup++) {
327 centralization_low_limit[pup] = ADLL_MIN;
328 centralization_high_limit[pup] = ADLL_MAX;
341 /* Prepare pup masks *
892 u32 pup; local
956 u32 pup; local
1117 u32 pup; local
1264 u32 pup, pup_num; local
[all...] |
| /external/u-boot/drivers/ddr/marvell/a38x/ |
| ddr3_training_hw_algo.c | 138 * pup.
160 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; local
182 for (pup = 0;
183 pup < octets_per_if_num; pup++) {
184 current_vref[pup][if_id] = 0;
185 last_vref[pup][if_id] = 0;
186 lim_vref[pup][if_id] = 0;
187 current_valid_window[pup][if_id] = 0;
188 last_valid_window[pup][if_id] = 0
[all...] |
| ddr3_training_pbs.c | 45 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local
83 for (pup = 0; pup < octets_per_if_num; pup++) {
84 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
87 min_adll_per_pup[if_id][pup] =
89 pup_state[if_id][pup] = 0x3;
90 adll_shift_lock[if_id][pup] = 1;
91 max_adll_per_pup[if_id][pup] = 0x0;
96 for (pup = 0; pup < octets_per_if_num; pup++)
939 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; local
989 u32 if_id, pup, bit; local
[all...] |
| ddr3_debug.c | 1310 u32 pup = 0, start_pup = 0, end_pup = 0; local
1456 u32 pup = 0, start_pup = 0, end_pup = 0, start_adll = 0; local
[all...] |
