1 /* 2 * Copyright 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric (at) anholt.net> 25 * 26 */ 27 28 #ifndef BRW_FS_H 29 #define BRW_FS_H 30 31 #include "brw_shader.h" 32 #include "brw_ir_fs.h" 33 #include "brw_fs_builder.h" 34 #include "compiler/nir/nir.h" 35 36 struct bblock_t; 37 namespace { 38 struct acp_entry; 39 } 40 41 namespace brw { 42 class fs_live_variables; 43 } 44 45 struct brw_gs_compile; 46 47 static inline fs_reg 48 offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta) 49 { 50 return offset(reg, bld.dispatch_width(), delta); 51 } 52 53 #define UBO_START ((1 << 16) - 4) 54 55 /** 56 * The fragment shader front-end. 57 * 58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. 59 */ 60 class fs_visitor : public backend_shader 61 { 62 public: 63 fs_visitor(const struct brw_compiler *compiler, void *log_data, 64 void *mem_ctx, 65 const void *key, 66 struct brw_stage_prog_data *prog_data, 67 struct gl_program *prog, 68 const nir_shader *shader, 69 unsigned dispatch_width, 70 int shader_time_index, 71 const struct brw_vue_map *input_vue_map = NULL); 72 fs_visitor(const struct brw_compiler *compiler, void *log_data, 73 void *mem_ctx, 74 struct brw_gs_compile *gs_compile, 75 struct brw_gs_prog_data *prog_data, 76 const nir_shader *shader, 77 int shader_time_index); 78 void init(); 79 ~fs_visitor(); 80 81 fs_reg vgrf(const glsl_type *const type); 82 void import_uniforms(fs_visitor *v); 83 void setup_uniform_clipplane_values(); 84 void compute_clip_distance(); 85 86 fs_inst *get_instruction_generating_reg(fs_inst *start, 87 fs_inst *end, 88 const fs_reg ®); 89 90 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld, 91 const fs_reg &dst, 92 const fs_reg &surf_index, 93 const fs_reg &varying_offset, 94 uint32_t const_offset); 95 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf); 96 97 bool run_fs(bool allow_spilling, bool do_rep_send); 98 bool run_vs(); 99 bool run_tcs_single_patch(); 100 bool run_tes(); 101 bool run_gs(); 102 bool run_cs(unsigned min_dispatch_width); 103 void optimize(); 104 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling); 105 void setup_fs_payload_gen4(); 106 void setup_fs_payload_gen6(); 107 void setup_vs_payload(); 108 void setup_gs_payload(); 109 void setup_cs_payload(); 110 void fixup_3src_null_dest(); 111 void assign_curb_setup(); 112 void calculate_urb_setup(); 113 void assign_urb_setup(); 114 void convert_attr_sources_to_hw_regs(fs_inst *inst); 115 void assign_vs_urb_setup(); 116 void assign_tcs_single_patch_urb_setup(); 117 void assign_tes_urb_setup(); 118 void assign_gs_urb_setup(); 119 bool assign_regs(bool allow_spilling, bool spill_all); 120 void assign_regs_trivial(); 121 void calculate_payload_ranges(int payload_node_count, 122 int *payload_last_use_ip); 123 void setup_payload_interference(struct ra_graph *g, int payload_reg_count, 124 int first_payload_node); 125 int choose_spill_reg(struct ra_graph *g); 126 void spill_reg(int spill_reg); 127 void split_virtual_grfs(); 128 bool compact_virtual_grfs(); 129 void assign_constant_locations(); 130 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index, 131 unsigned *out_pull_index); 132 void lower_constant_loads(); 133 void invalidate_live_intervals(); 134 void calculate_live_intervals(); 135 void calculate_register_pressure(); 136 void validate(); 137 bool opt_algebraic(); 138 bool opt_redundant_discard_jumps(); 139 bool opt_cse(); 140 bool opt_cse_local(bblock_t *block); 141 bool opt_copy_propagation(); 142 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry); 143 bool try_constant_propagate(fs_inst *inst, acp_entry *entry); 144 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block, 145 exec_list *acp); 146 bool opt_drop_redundant_mov_to_flags(); 147 bool opt_register_renaming(); 148 bool opt_bank_conflicts(); 149 unsigned bank_conflict_cycles(const fs_inst *inst) const; 150 bool register_coalesce(); 151 bool compute_to_mrf(); 152 bool eliminate_find_live_channel(); 153 bool dead_code_eliminate(); 154 bool remove_duplicate_mrf_writes(); 155 bool remove_extra_rounding_modes(); 156 157 bool opt_sampler_eot(); 158 bool virtual_grf_interferes(int a, int b); 159 void schedule_instructions(instruction_scheduler_mode mode); 160 void insert_gen4_send_dependency_workarounds(); 161 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block, 162 fs_inst *inst); 163 void insert_gen4_post_send_dependency_workarounds(bblock_t *block, 164 fs_inst *inst); 165 void vfail(const char *msg, va_list args); 166 void fail(const char *msg, ...); 167 void limit_dispatch_width(unsigned n, const char *msg); 168 void lower_uniform_pull_constant_loads(); 169 bool lower_load_payload(); 170 bool lower_pack(); 171 bool lower_conversions(); 172 bool lower_logical_sends(); 173 bool lower_integer_multiplication(); 174 bool lower_minmax(); 175 bool lower_simd_width(); 176 bool opt_combine_constants(); 177 178 void emit_dummy_fs(); 179 void emit_repclear_shader(); 180 void emit_fragcoord_interpolation(fs_reg wpos); 181 fs_reg *emit_frontfacing_interpolation(); 182 fs_reg *emit_samplepos_setup(); 183 fs_reg *emit_sampleid_setup(); 184 fs_reg *emit_samplemaskin_setup(); 185 void emit_interpolation_setup_gen4(); 186 void emit_interpolation_setup_gen6(); 187 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); 188 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components, 189 const fs_reg &sampler); 190 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst); 191 fs_reg resolve_source_modifiers(const fs_reg &src); 192 void emit_discard_jump(); 193 bool opt_peephole_sel(); 194 bool opt_peephole_predicated_break(); 195 bool opt_saturate_propagation(); 196 bool opt_cmod_propagation(); 197 bool opt_zero_samples(); 198 199 void emit_nir_code(); 200 void nir_setup_outputs(); 201 void nir_setup_uniforms(); 202 void nir_emit_system_values(); 203 void nir_emit_impl(nir_function_impl *impl); 204 void nir_emit_cf_list(exec_list *list); 205 void nir_emit_if(nir_if *if_stmt); 206 void nir_emit_loop(nir_loop *loop); 207 void nir_emit_block(nir_block *block); 208 void nir_emit_instr(nir_instr *instr); 209 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr); 210 void nir_emit_load_const(const brw::fs_builder &bld, 211 nir_load_const_instr *instr); 212 void nir_emit_vs_intrinsic(const brw::fs_builder &bld, 213 nir_intrinsic_instr *instr); 214 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld, 215 nir_intrinsic_instr *instr); 216 void nir_emit_gs_intrinsic(const brw::fs_builder &bld, 217 nir_intrinsic_instr *instr); 218 void nir_emit_fs_intrinsic(const brw::fs_builder &bld, 219 nir_intrinsic_instr *instr); 220 void nir_emit_cs_intrinsic(const brw::fs_builder &bld, 221 nir_intrinsic_instr *instr); 222 void nir_emit_intrinsic(const brw::fs_builder &bld, 223 nir_intrinsic_instr *instr); 224 void nir_emit_tes_intrinsic(const brw::fs_builder &bld, 225 nir_intrinsic_instr *instr); 226 void nir_emit_ssbo_atomic(const brw::fs_builder &bld, 227 int op, nir_intrinsic_instr *instr); 228 void nir_emit_shared_atomic(const brw::fs_builder &bld, 229 int op, nir_intrinsic_instr *instr); 230 void nir_emit_texture(const brw::fs_builder &bld, 231 nir_tex_instr *instr); 232 void nir_emit_jump(const brw::fs_builder &bld, 233 nir_jump_instr *instr); 234 fs_reg get_nir_src(const nir_src &src); 235 fs_reg get_nir_src_imm(const nir_src &src); 236 fs_reg get_nir_dest(const nir_dest &dest); 237 fs_reg get_nir_image_deref(const nir_deref_var *deref); 238 fs_reg get_indirect_offset(nir_intrinsic_instr *instr); 239 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst, 240 unsigned wr_mask); 241 242 bool optimize_extract_to_float(nir_alu_instr *instr, 243 const fs_reg &result); 244 bool optimize_frontfacing_ternary(nir_alu_instr *instr, 245 const fs_reg &result); 246 247 void emit_alpha_test(); 248 fs_inst *emit_single_fb_write(const brw::fs_builder &bld, 249 fs_reg color1, fs_reg color2, 250 fs_reg src0_alpha, unsigned components); 251 void emit_fb_writes(); 252 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld, 253 const fs_reg &dst, unsigned target); 254 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg()); 255 void set_gs_stream_control_data_bits(const fs_reg &vertex_count, 256 unsigned stream_id); 257 void emit_gs_control_data_bits(const fs_reg &vertex_count); 258 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src); 259 void emit_gs_vertex(const nir_src &vertex_count_nir_src, 260 unsigned stream_id); 261 void emit_gs_thread_end(); 262 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src, 263 unsigned base_offset, const nir_src &offset_src, 264 unsigned num_components, unsigned first_component); 265 void emit_cs_terminate(); 266 fs_reg *emit_cs_work_group_id_setup(); 267 268 void emit_barrier(); 269 270 void emit_shader_time_begin(); 271 void emit_shader_time_end(); 272 void SHADER_TIME_ADD(const brw::fs_builder &bld, 273 int shader_time_subindex, 274 fs_reg value); 275 276 fs_reg get_timestamp(const brw::fs_builder &bld); 277 278 struct brw_reg interp_reg(int location, int channel); 279 280 int implied_mrf_writes(fs_inst *inst) const; 281 282 virtual void dump_instructions(); 283 virtual void dump_instructions(const char *name); 284 void dump_instruction(backend_instruction *inst); 285 void dump_instruction(backend_instruction *inst, FILE *file); 286 287 const void *const key; 288 const struct brw_sampler_prog_key_data *key_tex; 289 290 struct brw_gs_compile *gs_compile; 291 292 struct brw_stage_prog_data *prog_data; 293 struct gl_program *prog; 294 295 const struct brw_vue_map *input_vue_map; 296 297 int *virtual_grf_start; 298 int *virtual_grf_end; 299 brw::fs_live_variables *live_intervals; 300 301 int *regs_live_at_ip; 302 303 /** Number of uniform variable components visited. */ 304 unsigned uniforms; 305 306 /** Byte-offset for the next available spot in the scratch space buffer. */ 307 unsigned last_scratch; 308 309 /** 310 * Array mapping UNIFORM register numbers to the pull parameter index, 311 * or -1 if this uniform register isn't being uploaded as a pull constant. 312 */ 313 int *pull_constant_loc; 314 315 /** 316 * Array mapping UNIFORM register numbers to the push parameter index, 317 * or -1 if this uniform register isn't being uploaded as a push constant. 318 */ 319 int *push_constant_loc; 320 321 fs_reg subgroup_id; 322 fs_reg frag_depth; 323 fs_reg frag_stencil; 324 fs_reg sample_mask; 325 fs_reg outputs[VARYING_SLOT_MAX]; 326 fs_reg dual_src_output; 327 int first_non_payload_grf; 328 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */ 329 unsigned max_grf; 330 331 fs_reg *nir_locals; 332 fs_reg *nir_ssa_values; 333 fs_reg *nir_system_values; 334 335 bool failed; 336 char *fail_msg; 337 338 /** Register numbers for thread payload fields. */ 339 struct thread_payload { 340 uint8_t source_depth_reg; 341 uint8_t source_w_reg; 342 uint8_t aa_dest_stencil_reg; 343 uint8_t dest_depth_reg; 344 uint8_t sample_pos_reg; 345 uint8_t sample_mask_in_reg; 346 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT]; 347 uint8_t local_invocation_id_reg; 348 349 /** The number of thread payload registers the hardware will supply. */ 350 uint8_t num_regs; 351 } payload; 352 353 bool source_depth_to_render_target; 354 bool runtime_check_aads_emit; 355 356 fs_reg pixel_x; 357 fs_reg pixel_y; 358 fs_reg wpos_w; 359 fs_reg pixel_w; 360 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT]; 361 fs_reg shader_start_time; 362 fs_reg userplane[MAX_CLIP_PLANES]; 363 fs_reg final_gs_vertex_count; 364 fs_reg control_data_bits; 365 fs_reg invocation_id; 366 367 unsigned grf_used; 368 bool spilled_any_registers; 369 370 const unsigned dispatch_width; /**< 8, 16 or 32 */ 371 unsigned max_dispatch_width; 372 373 int shader_time_index; 374 375 unsigned promoted_constants; 376 brw::fs_builder bld; 377 }; 378 379 /** 380 * The fragment shader code generator. 381 * 382 * Translates FS IR to actual i965 assembly code. 383 */ 384 class fs_generator 385 { 386 public: 387 fs_generator(const struct brw_compiler *compiler, void *log_data, 388 void *mem_ctx, 389 const void *key, 390 struct brw_stage_prog_data *prog_data, 391 unsigned promoted_constants, 392 bool runtime_check_aads_emit, 393 gl_shader_stage stage); 394 ~fs_generator(); 395 396 void enable_debug(const char *shader_name); 397 int generate_code(const cfg_t *cfg, int dispatch_width); 398 const unsigned *get_assembly(unsigned int *assembly_size); 399 400 private: 401 void fire_fb_write(fs_inst *inst, 402 struct brw_reg payload, 403 struct brw_reg implied_header, 404 GLuint nr); 405 void generate_fb_write(fs_inst *inst, struct brw_reg payload); 406 void generate_fb_read(fs_inst *inst, struct brw_reg dst, 407 struct brw_reg payload); 408 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload); 409 void generate_urb_write(fs_inst *inst, struct brw_reg payload); 410 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); 411 void generate_barrier(fs_inst *inst, struct brw_reg src); 412 void generate_linterp(fs_inst *inst, struct brw_reg dst, 413 struct brw_reg *src); 414 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, 415 struct brw_reg surface_index, 416 struct brw_reg sampler_index); 417 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst, 418 struct brw_reg src, 419 struct brw_reg surf_index); 420 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src); 421 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src); 422 void generate_scratch_write(fs_inst *inst, struct brw_reg src); 423 void generate_scratch_read(fs_inst *inst, struct brw_reg dst); 424 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst); 425 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, 426 struct brw_reg index, 427 struct brw_reg offset); 428 void generate_uniform_pull_constant_load_gen7(fs_inst *inst, 429 struct brw_reg dst, 430 struct brw_reg surf_index, 431 struct brw_reg payload); 432 void generate_varying_pull_constant_load_gen4(fs_inst *inst, 433 struct brw_reg dst, 434 struct brw_reg index); 435 void generate_varying_pull_constant_load_gen7(fs_inst *inst, 436 struct brw_reg dst, 437 struct brw_reg index, 438 struct brw_reg offset); 439 void generate_mov_dispatch_to_flags(fs_inst *inst); 440 441 void generate_pixel_interpolator_query(fs_inst *inst, 442 struct brw_reg dst, 443 struct brw_reg src, 444 struct brw_reg msg_data, 445 unsigned msg_type); 446 447 void generate_set_sample_id(fs_inst *inst, 448 struct brw_reg dst, 449 struct brw_reg src0, 450 struct brw_reg src1); 451 452 void generate_discard_jump(fs_inst *inst); 453 454 void generate_pack_half_2x16_split(fs_inst *inst, 455 struct brw_reg dst, 456 struct brw_reg x, 457 struct brw_reg y); 458 void generate_unpack_half_2x16_split(fs_inst *inst, 459 struct brw_reg dst, 460 struct brw_reg src); 461 462 void generate_shader_time_add(fs_inst *inst, 463 struct brw_reg payload, 464 struct brw_reg offset, 465 struct brw_reg value); 466 467 void generate_mov_indirect(fs_inst *inst, 468 struct brw_reg dst, 469 struct brw_reg reg, 470 struct brw_reg indirect_byte_offset); 471 472 bool patch_discard_jumps_to_fb_writes(); 473 474 const struct brw_compiler *compiler; 475 void *log_data; /* Passed to compiler->*_log functions */ 476 477 const struct gen_device_info *devinfo; 478 479 struct brw_codegen *p; 480 const void * const key; 481 struct brw_stage_prog_data * const prog_data; 482 483 unsigned dispatch_width; /**< 8, 16 or 32 */ 484 485 exec_list discard_halt_patches; 486 unsigned promoted_constants; 487 bool runtime_check_aads_emit; 488 bool debug_flag; 489 const char *shader_name; 490 gl_shader_stage stage; 491 void *mem_ctx; 492 }; 493 494 void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld, 495 const fs_reg &dst, 496 const fs_reg &src, 497 uint32_t components); 498 499 fs_reg shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld, 500 const fs_reg &src, 501 uint32_t components); 502 503 void shuffle_32bit_load_result_to_16bit_data(const brw::fs_builder &bld, 504 const fs_reg &dst, 505 const fs_reg &src, 506 uint32_t components); 507 508 void shuffle_16bit_data_for_32bit_write(const brw::fs_builder &bld, 509 const fs_reg &dst, 510 const fs_reg &src, 511 uint32_t components); 512 513 fs_reg setup_imm_df(const brw::fs_builder &bld, 514 double v); 515 516 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode, 517 nir_intrinsic_op op); 518 519 #endif /* BRW_FS_H */ 520
