1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. 4 * 5 * (C) Copyright 2003 6 * Gary Jennejohn, DENX Software Engineering <garyj (at) denx.de> 7 * Note: Part of this code has been derived from linux 8 * 9 */ 10 /* 11 * IMPORTANT NOTES 12 * 1 - this driver is intended for use with USB Mass Storage Devices 13 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! 14 */ 15 16 #include <config.h> 17 18 #ifdef CONFIG_USB_OHCI 19 20 /* #include <pci.h> no PCI on the AU1x00 */ 21 22 #include <common.h> 23 #include <malloc.h> 24 #include <asm/io.h> 25 #include <mach/au1x00.h> 26 #include <usb.h> 27 #include "au1x00_usb_ohci.h" 28 29 #define OHCI_USE_NPS /* force NoPowerSwitching mode */ 30 #define OHCI_VERBOSE_DEBUG /* not always helpful */ 31 #define OHCI_FILL_TRACE 32 33 #define USBH_ENABLE_BE (1<<0) 34 #define USBH_ENABLE_C (1<<1) 35 #define USBH_ENABLE_E (1<<2) 36 #define USBH_ENABLE_CE (1<<3) 37 #define USBH_ENABLE_RD (1<<4) 38 39 #ifdef __LITTLE_ENDIAN 40 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) 41 #else 42 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) 43 #endif 44 45 46 /* For initializing controller (mask in an HCFS mode too) */ 47 #define OHCI_CONTROL_INIT \ 48 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 49 50 #undef readl 51 #undef writel 52 53 #define readl(a) au_readl((long)(a)) 54 #define writel(v,a) au_writel((v),(int)(a)) 55 56 #define DEBUG 57 #ifdef DEBUG 58 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 59 #else 60 #define dbg(format, arg...) do {} while(0) 61 #endif /* DEBUG */ 62 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 63 #define SHOW_INFO 64 #ifdef SHOW_INFO 65 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 66 #else 67 #define info(format, arg...) do {} while(0) 68 #endif 69 70 #define m16_swap(x) swap_16(x) 71 #define m32_swap(x) swap_32(x) 72 73 /* global ohci_t */ 74 static ohci_t gohci; 75 /* this must be aligned to a 256 byte boundary */ 76 struct ohci_hcca ghcca[1]; 77 /* a pointer to the aligned storage */ 78 struct ohci_hcca *phcca; 79 /* this allocates EDs for all possible endpoints */ 80 struct ohci_device ohci_dev; 81 /* urb_priv */ 82 urb_priv_t urb_priv; 83 /* RHSC flag */ 84 int got_rhsc; 85 /* device which was disconnected */ 86 struct usb_device *devgone; 87 88 /*-------------------------------------------------------------------------*/ 89 90 /* AMD-756 (D2 rev) reports corrupt register contents in some cases. 91 * The erratum (#4) description is incorrect. AMD's workaround waits 92 * till some bits (mostly reserved) are clear; ok for all revs. 93 */ 94 #define OHCI_QUIRK_AMD756 0xabcd 95 #define read_roothub(hc, register, mask) ({ \ 96 u32 temp = readl (&hc->regs->roothub.register); \ 97 if (hc->flags & OHCI_QUIRK_AMD756) \ 98 while (temp & mask) \ 99 temp = readl (&hc->regs->roothub.register); \ 100 temp; }) 101 102 static u32 roothub_a (struct ohci *hc) 103 { return read_roothub (hc, a, 0xfc0fe000); } 104 static inline u32 roothub_b (struct ohci *hc) 105 { return readl (&hc->regs->roothub.b); } 106 static inline u32 roothub_status (struct ohci *hc) 107 { return readl (&hc->regs->roothub.status); } 108 static u32 roothub_portstatus (struct ohci *hc, int i) 109 { return read_roothub (hc, portstatus [i], 0xffe0fce0); } 110 111 112 /* forward declaration */ 113 static int hc_interrupt (void); 114 static void 115 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, 116 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); 117 118 /*-------------------------------------------------------------------------* 119 * URB support functions 120 *-------------------------------------------------------------------------*/ 121 122 /* free HCD-private data associated with this URB */ 123 124 static void urb_free_priv (urb_priv_t * urb) 125 { 126 int i; 127 int last; 128 struct td * td; 129 130 last = urb->length - 1; 131 if (last >= 0) { 132 for (i = 0; i <= last; i++) { 133 td = urb->td[i]; 134 if (td) { 135 td->usb_dev = NULL; 136 urb->td[i] = NULL; 137 } 138 } 139 } 140 } 141 142 /*-------------------------------------------------------------------------*/ 143 144 #ifdef DEBUG 145 static int sohci_get_current_frame_number (struct usb_device * dev); 146 147 /* debug| print the main components of an URB 148 * small: 0) header + data packets 1) just header */ 149 150 static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, 151 int transfer_len, struct devrequest * setup, char * str, int small) 152 { 153 urb_priv_t * purb = &urb_priv; 154 155 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", 156 str, 157 sohci_get_current_frame_number (dev), 158 usb_pipedevice (pipe), 159 usb_pipeendpoint (pipe), 160 usb_pipeout (pipe)? 'O': 'I', 161 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): 162 (usb_pipecontrol (pipe)? "CTRL": "BULK"), 163 purb->actual_length, 164 transfer_len, dev->status); 165 #ifdef OHCI_VERBOSE_DEBUG 166 if (!small) { 167 int i, len; 168 169 if (usb_pipecontrol (pipe)) { 170 printf (__FILE__ ": cmd(8):"); 171 for (i = 0; i < 8 ; i++) 172 printf (" %02x", ((__u8 *) setup) [i]); 173 printf ("\n"); 174 } 175 if (transfer_len > 0 && buffer) { 176 printf (__FILE__ ": data(%d/%d):", 177 purb->actual_length, 178 transfer_len); 179 len = usb_pipeout (pipe)? 180 transfer_len: purb->actual_length; 181 for (i = 0; i < 16 && i < len; i++) 182 printf (" %02x", ((__u8 *) buffer) [i]); 183 printf ("%s\n", i < len? "...": ""); 184 } 185 } 186 #endif 187 } 188 189 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ 190 void ep_print_int_eds (ohci_t *ohci, char * str) { 191 int i, j; 192 __u32 * ed_p; 193 for (i= 0; i < 32; i++) { 194 j = 5; 195 ed_p = &(ohci->hcca->int_table [i]); 196 if (*ed_p == 0) 197 continue; 198 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); 199 while (*ed_p != 0 && j--) { 200 ed_t *ed = (ed_t *)m32_swap(ed_p); 201 printf (" ed: %4x;", ed->hwINFO); 202 ed_p = &ed->hwNextED; 203 } 204 printf ("\n"); 205 } 206 } 207 208 static void ohci_dump_intr_mask (char *label, __u32 mask) 209 { 210 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 211 label, 212 mask, 213 (mask & OHCI_INTR_MIE) ? " MIE" : "", 214 (mask & OHCI_INTR_OC) ? " OC" : "", 215 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 216 (mask & OHCI_INTR_FNO) ? " FNO" : "", 217 (mask & OHCI_INTR_UE) ? " UE" : "", 218 (mask & OHCI_INTR_RD) ? " RD" : "", 219 (mask & OHCI_INTR_SF) ? " SF" : "", 220 (mask & OHCI_INTR_WDH) ? " WDH" : "", 221 (mask & OHCI_INTR_SO) ? " SO" : "" 222 ); 223 } 224 225 static void maybe_print_eds (char *label, __u32 value) 226 { 227 ed_t *edp = (ed_t *)value; 228 229 if (value) { 230 dbg ("%s %08x", label, value); 231 dbg ("%08x", edp->hwINFO); 232 dbg ("%08x", edp->hwTailP); 233 dbg ("%08x", edp->hwHeadP); 234 dbg ("%08x", edp->hwNextED); 235 } 236 } 237 238 static char * hcfs2string (int state) 239 { 240 switch (state) { 241 case OHCI_USB_RESET: return "reset"; 242 case OHCI_USB_RESUME: return "resume"; 243 case OHCI_USB_OPER: return "operational"; 244 case OHCI_USB_SUSPEND: return "suspend"; 245 } 246 return "?"; 247 } 248 249 /* dump control and status registers */ 250 static void ohci_dump_status (ohci_t *controller) 251 { 252 struct ohci_regs *regs = controller->regs; 253 __u32 temp; 254 255 temp = readl (®s->revision) & 0xff; 256 if (temp != 0x10) 257 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); 258 259 temp = readl (®s->control); 260 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 261 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 262 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 263 (temp & OHCI_CTRL_IR) ? " IR" : "", 264 hcfs2string (temp & OHCI_CTRL_HCFS), 265 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 266 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 267 (temp & OHCI_CTRL_IE) ? " IE" : "", 268 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 269 temp & OHCI_CTRL_CBSR 270 ); 271 272 temp = readl (®s->cmdstatus); 273 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 274 (temp & OHCI_SOC) >> 16, 275 (temp & OHCI_OCR) ? " OCR" : "", 276 (temp & OHCI_BLF) ? " BLF" : "", 277 (temp & OHCI_CLF) ? " CLF" : "", 278 (temp & OHCI_HCR) ? " HCR" : "" 279 ); 280 281 ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); 282 ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); 283 284 maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); 285 286 maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); 287 maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); 288 289 maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); 290 maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); 291 292 maybe_print_eds ("donehead", readl (®s->donehead)); 293 } 294 295 static void ohci_dump_roothub (ohci_t *controller, int verbose) 296 { 297 __u32 temp, ndp, i; 298 299 temp = roothub_a (controller); 300 ndp = (temp & RH_A_NDP); 301 302 if (verbose) { 303 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 304 ((temp & RH_A_POTPGT) >> 24) & 0xff, 305 (temp & RH_A_NOCP) ? " NOCP" : "", 306 (temp & RH_A_OCPM) ? " OCPM" : "", 307 (temp & RH_A_DT) ? " DT" : "", 308 (temp & RH_A_NPS) ? " NPS" : "", 309 (temp & RH_A_PSM) ? " PSM" : "", 310 ndp 311 ); 312 temp = roothub_b (controller); 313 dbg ("roothub.b: %08x PPCM=%04x DR=%04x", 314 temp, 315 (temp & RH_B_PPCM) >> 16, 316 (temp & RH_B_DR) 317 ); 318 temp = roothub_status (controller); 319 dbg ("roothub.status: %08x%s%s%s%s%s%s", 320 temp, 321 (temp & RH_HS_CRWE) ? " CRWE" : "", 322 (temp & RH_HS_OCIC) ? " OCIC" : "", 323 (temp & RH_HS_LPSC) ? " LPSC" : "", 324 (temp & RH_HS_DRWE) ? " DRWE" : "", 325 (temp & RH_HS_OCI) ? " OCI" : "", 326 (temp & RH_HS_LPS) ? " LPS" : "" 327 ); 328 } 329 330 for (i = 0; i < ndp; i++) { 331 temp = roothub_portstatus (controller, i); 332 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 333 i, 334 temp, 335 (temp & RH_PS_PRSC) ? " PRSC" : "", 336 (temp & RH_PS_OCIC) ? " OCIC" : "", 337 (temp & RH_PS_PSSC) ? " PSSC" : "", 338 (temp & RH_PS_PESC) ? " PESC" : "", 339 (temp & RH_PS_CSC) ? " CSC" : "", 340 341 (temp & RH_PS_LSDA) ? " LSDA" : "", 342 (temp & RH_PS_PPS) ? " PPS" : "", 343 (temp & RH_PS_PRS) ? " PRS" : "", 344 (temp & RH_PS_POCI) ? " POCI" : "", 345 (temp & RH_PS_PSS) ? " PSS" : "", 346 347 (temp & RH_PS_PES) ? " PES" : "", 348 (temp & RH_PS_CCS) ? " CCS" : "" 349 ); 350 } 351 } 352 353 static void ohci_dump (ohci_t *controller, int verbose) 354 { 355 dbg ("OHCI controller usb-%s state", controller->slot_name); 356 357 /* dumps some of the state we know about */ 358 ohci_dump_status (controller); 359 if (verbose) 360 ep_print_int_eds (controller, "hcca"); 361 dbg ("hcca frame #%04x", controller->hcca->frame_no); 362 ohci_dump_roothub (controller, 1); 363 } 364 365 366 #endif /* DEBUG */ 367 368 /*-------------------------------------------------------------------------* 369 * Interface functions (URB) 370 *-------------------------------------------------------------------------*/ 371 372 /* get a transfer request */ 373 374 int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, 375 int transfer_len, struct devrequest *setup, int interval) 376 { 377 ohci_t *ohci; 378 ed_t * ed; 379 urb_priv_t *purb_priv; 380 int i, size = 0; 381 382 ohci = &gohci; 383 384 /* when controller's hung, permit only roothub cleanup attempts 385 * such as powering down ports */ 386 if (ohci->disabled) { 387 err("sohci_submit_job: EPIPE"); 388 return -1; 389 } 390 391 /* every endpoint has a ed, locate and fill it */ 392 if (!(ed = ep_add_ed (dev, pipe))) { 393 err("sohci_submit_job: ENOMEM"); 394 return -1; 395 } 396 397 /* for the private part of the URB we need the number of TDs (size) */ 398 switch (usb_pipetype (pipe)) { 399 case PIPE_BULK: /* one TD for every 4096 Byte */ 400 size = (transfer_len - 1) / 4096 + 1; 401 break; 402 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 403 size = (transfer_len == 0)? 2: 404 (transfer_len - 1) / 4096 + 3; 405 break; 406 } 407 408 if (size >= (N_URB_TD - 1)) { 409 err("need %d TDs, only have %d", size, N_URB_TD); 410 return -1; 411 } 412 purb_priv = &urb_priv; 413 purb_priv->pipe = pipe; 414 415 /* fill the private part of the URB */ 416 purb_priv->length = size; 417 purb_priv->ed = ed; 418 purb_priv->actual_length = 0; 419 420 /* allocate the TDs */ 421 /* note that td[0] was allocated in ep_add_ed */ 422 for (i = 0; i < size; i++) { 423 purb_priv->td[i] = td_alloc (dev); 424 if (!purb_priv->td[i]) { 425 purb_priv->length = i; 426 urb_free_priv (purb_priv); 427 err("sohci_submit_job: ENOMEM"); 428 return -1; 429 } 430 } 431 432 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 433 urb_free_priv (purb_priv); 434 err("sohci_submit_job: EINVAL"); 435 return -1; 436 } 437 438 /* link the ed into a chain if is not already */ 439 if (ed->state != ED_OPER) 440 ep_link (ohci, ed); 441 442 /* fill the TDs and link it to the ed */ 443 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); 444 445 return 0; 446 } 447 448 /*-------------------------------------------------------------------------*/ 449 450 #ifdef DEBUG 451 /* tell us the current USB frame number */ 452 453 static int sohci_get_current_frame_number (struct usb_device *usb_dev) 454 { 455 ohci_t *ohci = &gohci; 456 457 return m16_swap (ohci->hcca->frame_no); 458 } 459 #endif 460 461 /*-------------------------------------------------------------------------* 462 * ED handling functions 463 *-------------------------------------------------------------------------*/ 464 465 /* link an ed into one of the HC chains */ 466 467 static int ep_link (ohci_t *ohci, ed_t *edi) 468 { 469 volatile ed_t *ed = edi; 470 471 ed->state = ED_OPER; 472 473 switch (ed->type) { 474 case PIPE_CONTROL: 475 ed->hwNextED = 0; 476 if (ohci->ed_controltail == NULL) { 477 writel ((long)ed, &ohci->regs->ed_controlhead); 478 } else { 479 ohci->ed_controltail->hwNextED = m32_swap (ed); 480 } 481 ed->ed_prev = ohci->ed_controltail; 482 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 483 !ohci->ed_rm_list[1] && !ohci->sleeping) { 484 ohci->hc_control |= OHCI_CTRL_CLE; 485 writel (ohci->hc_control, &ohci->regs->control); 486 } 487 ohci->ed_controltail = edi; 488 break; 489 490 case PIPE_BULK: 491 ed->hwNextED = 0; 492 if (ohci->ed_bulktail == NULL) { 493 writel ((long)ed, &ohci->regs->ed_bulkhead); 494 } else { 495 ohci->ed_bulktail->hwNextED = m32_swap (ed); 496 } 497 ed->ed_prev = ohci->ed_bulktail; 498 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 499 !ohci->ed_rm_list[1] && !ohci->sleeping) { 500 ohci->hc_control |= OHCI_CTRL_BLE; 501 writel (ohci->hc_control, &ohci->regs->control); 502 } 503 ohci->ed_bulktail = edi; 504 break; 505 } 506 return 0; 507 } 508 509 /*-------------------------------------------------------------------------*/ 510 511 /* unlink an ed from one of the HC chains. 512 * just the link to the ed is unlinked. 513 * the link from the ed still points to another operational ed or 0 514 * so the HC can eventually finish the processing of the unlinked ed */ 515 516 static int ep_unlink (ohci_t *ohci, ed_t *ed) 517 { 518 ed->hwINFO |= m32_swap (OHCI_ED_SKIP); 519 520 switch (ed->type) { 521 case PIPE_CONTROL: 522 if (ed->ed_prev == NULL) { 523 if (!ed->hwNextED) { 524 ohci->hc_control &= ~OHCI_CTRL_CLE; 525 writel (ohci->hc_control, &ohci->regs->control); 526 } 527 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); 528 } else { 529 ed->ed_prev->hwNextED = ed->hwNextED; 530 } 531 if (ohci->ed_controltail == ed) { 532 ohci->ed_controltail = ed->ed_prev; 533 } else { 534 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 535 } 536 break; 537 538 case PIPE_BULK: 539 if (ed->ed_prev == NULL) { 540 if (!ed->hwNextED) { 541 ohci->hc_control &= ~OHCI_CTRL_BLE; 542 writel (ohci->hc_control, &ohci->regs->control); 543 } 544 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); 545 } else { 546 ed->ed_prev->hwNextED = ed->hwNextED; 547 } 548 if (ohci->ed_bulktail == ed) { 549 ohci->ed_bulktail = ed->ed_prev; 550 } else { 551 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 552 } 553 break; 554 } 555 ed->state = ED_UNLINK; 556 return 0; 557 } 558 559 560 /*-------------------------------------------------------------------------*/ 561 562 /* add/reinit an endpoint; this should be done once at the usb_set_configuration command, 563 * but the USB stack is a little bit stateless so we do it at every transaction 564 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK 565 * in all other cases the state is left unchanged 566 * the ed info fields are setted anyway even though most of them should not change */ 567 568 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) 569 { 570 td_t *td; 571 ed_t *ed_ret; 572 volatile ed_t *ed; 573 574 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | 575 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; 576 577 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 578 err("ep_add_ed: pending delete"); 579 /* pending delete request */ 580 return NULL; 581 } 582 583 if (ed->state == ED_NEW) { 584 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ 585 /* dummy td; end of td list for ed */ 586 td = td_alloc (usb_dev); 587 ed->hwTailP = m32_swap (td); 588 ed->hwHeadP = ed->hwTailP; 589 ed->state = ED_UNLINK; 590 ed->type = usb_pipetype (pipe); 591 ohci_dev.ed_cnt++; 592 } 593 594 ed->hwINFO = m32_swap (usb_pipedevice (pipe) 595 | usb_pipeendpoint (pipe) << 7 596 | (usb_pipeisoc (pipe)? 0x8000: 0) 597 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) 598 | (usb_dev->speed == USB_SPEED_LOW) << 13 599 | usb_maxpacket (usb_dev, pipe) << 16); 600 601 return ed_ret; 602 } 603 604 /*-------------------------------------------------------------------------* 605 * TD handling functions 606 *-------------------------------------------------------------------------*/ 607 608 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 609 610 static void td_fill (ohci_t *ohci, unsigned int info, 611 void *data, int len, 612 struct usb_device *dev, int index, urb_priv_t *urb_priv) 613 { 614 volatile td_t *td, *td_pt; 615 #ifdef OHCI_FILL_TRACE 616 int i; 617 #endif 618 619 if (index > urb_priv->length) { 620 err("index > length"); 621 return; 622 } 623 /* use this td as the next dummy */ 624 td_pt = urb_priv->td [index]; 625 td_pt->hwNextTD = 0; 626 627 /* fill the old dummy TD */ 628 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); 629 630 td->ed = urb_priv->ed; 631 td->next_dl_td = NULL; 632 td->index = index; 633 td->data = (__u32)data; 634 #ifdef OHCI_FILL_TRACE 635 if (1 || (usb_pipebulk(urb_priv->pipe) && 636 usb_pipeout(urb_priv->pipe))) { 637 for (i = 0; i < len; i++) 638 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]); 639 } 640 #endif 641 if (!len) 642 data = 0; 643 644 td->hwINFO = m32_swap (info); 645 td->hwCBP = m32_swap (data); 646 if (data) 647 td->hwBE = m32_swap (data + len - 1); 648 else 649 td->hwBE = 0; 650 td->hwNextTD = m32_swap (td_pt); 651 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); 652 653 /* append to queue */ 654 td->ed->hwTailP = td->hwNextTD; 655 } 656 657 /*-------------------------------------------------------------------------*/ 658 659 /* prepare all TDs of a transfer */ 660 661 #define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000)) 662 663 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, 664 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) 665 { 666 ohci_t *ohci = &gohci; 667 int data_len = transfer_len; 668 void *data; 669 int cnt = 0; 670 __u32 info = 0; 671 unsigned int toggle = 0; 672 673 /* OHCI handles the DATA-toggles itself, we just use the 674 USB-toggle bits for resetting */ 675 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 676 toggle = TD_T_TOGGLE; 677 } else { 678 toggle = TD_T_DATA0; 679 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); 680 } 681 urb->td_cnt = 0; 682 if (data_len) 683 data = kseg_to_phys(buffer); 684 else 685 data = 0; 686 687 switch (usb_pipetype (pipe)) { 688 case PIPE_BULK: 689 info = usb_pipeout (pipe)? 690 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 691 while(data_len > 4096) { 692 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); 693 data += 4096; data_len -= 4096; cnt++; 694 } 695 info = usb_pipeout (pipe)? 696 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 697 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); 698 cnt++; 699 700 if (!ohci->sleeping) 701 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ 702 break; 703 704 case PIPE_CONTROL: 705 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 706 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb); 707 if (data_len > 0) { 708 info = usb_pipeout (pipe)? 709 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 710 /* NOTE: mishandles transfers >8K, some >4K */ 711 td_fill (ohci, info, data, data_len, dev, cnt++, urb); 712 } 713 info = usb_pipeout (pipe)? 714 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; 715 td_fill (ohci, info, data, 0, dev, cnt++, urb); 716 if (!ohci->sleeping) 717 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ 718 break; 719 } 720 if (urb->length != cnt) 721 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 722 } 723 724 /*-------------------------------------------------------------------------* 725 * Done List handling functions 726 *-------------------------------------------------------------------------*/ 727 728 729 /* calculate the transfer length and update the urb */ 730 731 static void dl_transfer_length(td_t * td) 732 { 733 __u32 tdINFO, tdBE, tdCBP; 734 urb_priv_t *lurb_priv = &urb_priv; 735 736 tdINFO = m32_swap (td->hwINFO); 737 tdBE = m32_swap (td->hwBE); 738 tdCBP = m32_swap (td->hwCBP); 739 740 741 if (!(usb_pipecontrol(lurb_priv->pipe) && 742 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 743 if (tdBE != 0) { 744 if (td->hwCBP == 0) 745 lurb_priv->actual_length += tdBE - td->data + 1; 746 else 747 lurb_priv->actual_length += tdCBP - td->data; 748 } 749 } 750 } 751 752 /*-------------------------------------------------------------------------*/ 753 754 /* replies to the request have to be on a FIFO basis so 755 * we reverse the reversed done-list */ 756 757 static td_t * dl_reverse_done_list (ohci_t *ohci) 758 { 759 __u32 td_list_hc; 760 td_t *td_rev = NULL; 761 td_t *td_list = NULL; 762 urb_priv_t *lurb_priv = NULL; 763 764 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; 765 ohci->hcca->done_head = 0; 766 767 while (td_list_hc) { 768 td_list = (td_t *)td_list_hc; 769 770 if (TD_CC_GET (m32_swap (td_list->hwINFO))) { 771 lurb_priv = &urb_priv; 772 dbg(" USB-error/status: %x : %p", 773 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); 774 if (td_list->ed->hwHeadP & m32_swap (0x1)) { 775 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { 776 td_list->ed->hwHeadP = 777 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | 778 (td_list->ed->hwHeadP & m32_swap (0x2)); 779 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; 780 } else 781 td_list->ed->hwHeadP &= m32_swap (0xfffffff2); 782 } 783 } 784 785 td_list->next_dl_td = td_rev; 786 td_rev = td_list; 787 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; 788 } 789 return td_list; 790 } 791 792 /*-------------------------------------------------------------------------*/ 793 794 /* td done list */ 795 static int dl_done_list (ohci_t *ohci, td_t *td_list) 796 { 797 td_t *td_list_next = NULL; 798 ed_t *ed; 799 int cc = 0; 800 int stat = 0; 801 /* urb_t *urb; */ 802 urb_priv_t *lurb_priv; 803 __u32 tdINFO, edHeadP, edTailP; 804 805 while (td_list) { 806 td_list_next = td_list->next_dl_td; 807 808 lurb_priv = &urb_priv; 809 tdINFO = m32_swap (td_list->hwINFO); 810 811 ed = td_list->ed; 812 813 dl_transfer_length(td_list); 814 815 /* error code of transfer */ 816 cc = TD_CC_GET (tdINFO); 817 if (cc != 0) { 818 dbg("ConditionCode %#x", cc); 819 stat = cc_to_error[cc]; 820 } 821 822 if (ed->state != ED_NEW) { 823 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; 824 edTailP = m32_swap (ed->hwTailP); 825 826 /* unlink eds if they are not busy */ 827 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 828 ep_unlink (ohci, ed); 829 } 830 831 td_list = td_list_next; 832 } 833 return stat; 834 } 835 836 /*-------------------------------------------------------------------------* 837 * Virtual Root Hub 838 *-------------------------------------------------------------------------*/ 839 840 #include <usbroothubdes.h> 841 842 /* Hub class-specific descriptor is constructed dynamically */ 843 844 845 /*-------------------------------------------------------------------------*/ 846 847 #define OK(x) len = (x); break 848 #ifdef DEBUG 849 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} 850 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} 851 #else 852 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) 853 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) 854 #endif 855 #define RD_RH_STAT roothub_status(&gohci) 856 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) 857 858 /* request to virtual root hub */ 859 860 int rh_check_port_status(ohci_t *controller) 861 { 862 __u32 temp, ndp, i; 863 int res; 864 865 res = -1; 866 temp = roothub_a (controller); 867 ndp = (temp & RH_A_NDP); 868 for (i = 0; i < ndp; i++) { 869 temp = roothub_portstatus (controller, i); 870 /* check for a device disconnect */ 871 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 872 (RH_PS_PESC | RH_PS_CSC)) && 873 ((temp & RH_PS_CCS) == 0)) { 874 res = i; 875 break; 876 } 877 } 878 return res; 879 } 880 881 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, 882 void *buffer, int transfer_len, struct devrequest *cmd) 883 { 884 void * data = buffer; 885 int leni = transfer_len; 886 int len = 0; 887 int stat = 0; 888 __u32 datab[4]; 889 __u8 *data_buf = (__u8 *)datab; 890 __u16 bmRType_bReq; 891 __u16 wValue; 892 __u16 wIndex; 893 __u16 wLength; 894 895 #ifdef DEBUG 896 urb_priv.actual_length = 0; 897 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); 898 #else 899 mdelay(1); 900 #endif 901 if (usb_pipeint(pipe)) { 902 info("Root-Hub submit IRQ: NOT implemented"); 903 return 0; 904 } 905 906 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 907 wValue = m16_swap (cmd->value); 908 wIndex = m16_swap (cmd->index); 909 wLength = m16_swap (cmd->length); 910 911 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 912 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 913 914 switch (bmRType_bReq) { 915 /* Request Destination: 916 without flags: Device, 917 RH_INTERFACE: interface, 918 RH_ENDPOINT: endpoint, 919 RH_CLASS means HUB here, 920 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 921 */ 922 923 case RH_GET_STATUS: 924 *(__u16 *) data_buf = m16_swap (1); OK (2); 925 case RH_GET_STATUS | RH_INTERFACE: 926 *(__u16 *) data_buf = m16_swap (0); OK (2); 927 case RH_GET_STATUS | RH_ENDPOINT: 928 *(__u16 *) data_buf = m16_swap (0); OK (2); 929 case RH_GET_STATUS | RH_CLASS: 930 *(__u32 *) data_buf = m32_swap ( 931 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 932 OK (4); 933 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 934 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); 935 936 case RH_CLEAR_FEATURE | RH_ENDPOINT: 937 switch (wValue) { 938 case (RH_ENDPOINT_STALL): OK (0); 939 } 940 break; 941 942 case RH_CLEAR_FEATURE | RH_CLASS: 943 switch (wValue) { 944 case RH_C_HUB_LOCAL_POWER: 945 OK(0); 946 case (RH_C_HUB_OVER_CURRENT): 947 WR_RH_STAT(RH_HS_OCIC); OK (0); 948 } 949 break; 950 951 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 952 switch (wValue) { 953 case (RH_PORT_ENABLE): 954 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); 955 case (RH_PORT_SUSPEND): 956 WR_RH_PORTSTAT (RH_PS_POCI); OK (0); 957 case (RH_PORT_POWER): 958 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); 959 case (RH_C_PORT_CONNECTION): 960 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); 961 case (RH_C_PORT_ENABLE): 962 WR_RH_PORTSTAT (RH_PS_PESC); OK (0); 963 case (RH_C_PORT_SUSPEND): 964 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); 965 case (RH_C_PORT_OVER_CURRENT): 966 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); 967 case (RH_C_PORT_RESET): 968 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); 969 } 970 break; 971 972 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 973 switch (wValue) { 974 case (RH_PORT_SUSPEND): 975 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); 976 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 977 if (RD_RH_PORTSTAT & RH_PS_CCS) 978 WR_RH_PORTSTAT (RH_PS_PRS); 979 OK (0); 980 case (RH_PORT_POWER): 981 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); 982 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 983 if (RD_RH_PORTSTAT & RH_PS_CCS) 984 WR_RH_PORTSTAT (RH_PS_PES ); 985 OK (0); 986 } 987 break; 988 989 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); 990 991 case RH_GET_DESCRIPTOR: 992 switch ((wValue & 0xff00) >> 8) { 993 case (0x01): /* device descriptor */ 994 len = min_t(unsigned int, 995 leni, 996 min_t(unsigned int, 997 sizeof (root_hub_dev_des), 998 wLength)); 999 data_buf = root_hub_dev_des; OK(len); 1000 case (0x02): /* configuration descriptor */ 1001 len = min_t(unsigned int, 1002 leni, 1003 min_t(unsigned int, 1004 sizeof (root_hub_config_des), 1005 wLength)); 1006 data_buf = root_hub_config_des; OK(len); 1007 case (0x03): /* string descriptors */ 1008 if(wValue==0x0300) { 1009 len = min_t(unsigned int, 1010 leni, 1011 min_t(unsigned int, 1012 sizeof (root_hub_str_index0), 1013 wLength)); 1014 data_buf = root_hub_str_index0; 1015 OK(len); 1016 } 1017 if(wValue==0x0301) { 1018 len = min_t(unsigned int, 1019 leni, 1020 min_t(unsigned int, 1021 sizeof (root_hub_str_index1), 1022 wLength)); 1023 data_buf = root_hub_str_index1; 1024 OK(len); 1025 } 1026 default: 1027 stat = USB_ST_STALLED; 1028 } 1029 break; 1030 1031 case RH_GET_DESCRIPTOR | RH_CLASS: 1032 { 1033 __u32 temp = roothub_a (&gohci); 1034 1035 data_buf [0] = 9; /* min length; */ 1036 data_buf [1] = 0x29; 1037 data_buf [2] = temp & RH_A_NDP; 1038 data_buf [3] = 0; 1039 if (temp & RH_A_PSM) /* per-port power switching? */ 1040 data_buf [3] |= 0x1; 1041 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1042 data_buf [3] |= 0x10; 1043 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ 1044 data_buf [3] |= 0x8; 1045 1046 /* corresponds to data_buf[4-7] */ 1047 datab [1] = 0; 1048 data_buf [5] = (temp & RH_A_POTPGT) >> 24; 1049 temp = roothub_b (&gohci); 1050 data_buf [7] = temp & RH_B_DR; 1051 if (data_buf [2] < 7) { 1052 data_buf [8] = 0xff; 1053 } else { 1054 data_buf [0] += 2; 1055 data_buf [8] = (temp & RH_B_DR) >> 8; 1056 data_buf [10] = data_buf [9] = 0xff; 1057 } 1058 1059 len = min_t(unsigned int, leni, 1060 min_t(unsigned int, data_buf [0], wLength)); 1061 OK (len); 1062 } 1063 1064 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); 1065 1066 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); 1067 1068 default: 1069 dbg ("unsupported root hub command"); 1070 stat = USB_ST_STALLED; 1071 } 1072 1073 #ifdef DEBUG 1074 ohci_dump_roothub (&gohci, 1); 1075 #else 1076 mdelay(1); 1077 #endif 1078 1079 len = min_t(int, len, leni); 1080 if (data != data_buf) 1081 memcpy (data, data_buf, len); 1082 dev->act_len = len; 1083 dev->status = stat; 1084 1085 #ifdef DEBUG 1086 if (transfer_len) 1087 urb_priv.actual_length = transfer_len; 1088 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1089 #else 1090 mdelay(1); 1091 #endif 1092 1093 return stat; 1094 } 1095 1096 /*-------------------------------------------------------------------------*/ 1097 1098 /* common code for handling submit messages - used for all but root hub */ 1099 /* accesses. */ 1100 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1101 int transfer_len, struct devrequest *setup, int interval) 1102 { 1103 int stat = 0; 1104 int maxsize = usb_maxpacket(dev, pipe); 1105 int timeout; 1106 1107 /* device pulled? Shortcut the action. */ 1108 if (devgone == dev) { 1109 dev->status = USB_ST_CRC_ERR; 1110 return 0; 1111 } 1112 1113 #ifdef DEBUG 1114 urb_priv.actual_length = 0; 1115 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); 1116 #else 1117 mdelay(1); 1118 #endif 1119 if (!maxsize) { 1120 err("submit_common_message: pipesize for pipe %lx is zero", 1121 pipe); 1122 return -1; 1123 } 1124 1125 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { 1126 err("sohci_submit_job failed"); 1127 return -1; 1128 } 1129 1130 mdelay(10); 1131 /* ohci_dump_status(&gohci); */ 1132 1133 /* allow more time for a BULK device to react - some are slow */ 1134 #define BULK_TO 5000 /* timeout in milliseconds */ 1135 if (usb_pipebulk(pipe)) 1136 timeout = BULK_TO; 1137 else 1138 timeout = 100; 1139 1140 timeout *= 4; 1141 /* wait for it to complete */ 1142 for (;;) { 1143 /* check whether the controller is done */ 1144 stat = hc_interrupt(); 1145 if (stat < 0) { 1146 stat = USB_ST_CRC_ERR; 1147 break; 1148 } 1149 if (stat >= 0 && stat != 0xff) { 1150 /* 0xff is returned for an SF-interrupt */ 1151 break; 1152 } 1153 if (--timeout) { 1154 udelay(250); /* mdelay(1); */ 1155 } else { 1156 err("CTL:TIMEOUT "); 1157 stat = USB_ST_CRC_ERR; 1158 break; 1159 } 1160 } 1161 /* we got an Root Hub Status Change interrupt */ 1162 if (got_rhsc) { 1163 #ifdef DEBUG 1164 ohci_dump_roothub (&gohci, 1); 1165 #endif 1166 got_rhsc = 0; 1167 /* abuse timeout */ 1168 timeout = rh_check_port_status(&gohci); 1169 if (timeout >= 0) { 1170 #if 0 /* this does nothing useful, but leave it here in case that changes */ 1171 /* the called routine adds 1 to the passed value */ 1172 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); 1173 #endif 1174 /* 1175 * XXX 1176 * This is potentially dangerous because it assumes 1177 * that only one device is ever plugged in! 1178 */ 1179 devgone = dev; 1180 } 1181 } 1182 1183 dev->status = stat; 1184 dev->act_len = transfer_len; 1185 1186 #ifdef DEBUG 1187 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); 1188 #else 1189 mdelay(1); 1190 #endif 1191 1192 /* free TDs in urb_priv */ 1193 urb_free_priv (&urb_priv); 1194 return 0; 1195 } 1196 1197 /* submit routines called from usb.c */ 1198 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1199 int transfer_len) 1200 { 1201 info("submit_bulk_msg"); 1202 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); 1203 } 1204 1205 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1206 int transfer_len, struct devrequest *setup) 1207 { 1208 int maxsize = usb_maxpacket(dev, pipe); 1209 1210 info("submit_control_msg"); 1211 #ifdef DEBUG 1212 urb_priv.actual_length = 0; 1213 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); 1214 #else 1215 mdelay(1); 1216 #endif 1217 if (!maxsize) { 1218 err("submit_control_message: pipesize for pipe %lx is zero", 1219 pipe); 1220 return -1; 1221 } 1222 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { 1223 gohci.rh.dev = dev; 1224 /* root hub - redirect */ 1225 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, 1226 setup); 1227 } 1228 1229 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); 1230 } 1231 1232 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1233 int transfer_len, int interval) 1234 { 1235 info("submit_int_msg"); 1236 return -1; 1237 } 1238 1239 /*-------------------------------------------------------------------------* 1240 * HC functions 1241 *-------------------------------------------------------------------------*/ 1242 1243 /* reset the HC and BUS */ 1244 1245 static int hc_reset (ohci_t *ohci) 1246 { 1247 int timeout = 30; 1248 int smm_timeout = 50; /* 0,5 sec */ 1249 1250 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ 1251 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ 1252 info("USB HC TakeOver from SMM"); 1253 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { 1254 mdelay (10); 1255 if (--smm_timeout == 0) { 1256 err("USB HC TakeOver failed!"); 1257 return -1; 1258 } 1259 } 1260 } 1261 1262 /* Disable HC interrupts */ 1263 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); 1264 1265 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", 1266 ohci->slot_name, 1267 readl (&ohci->regs->control)); 1268 1269 /* Reset USB (needed by some controllers) */ 1270 writel (0, &ohci->regs->control); 1271 1272 /* HC Reset requires max 10 us delay */ 1273 writel (OHCI_HCR, &ohci->regs->cmdstatus); 1274 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1275 if (--timeout == 0) { 1276 err("USB HC reset timed out!"); 1277 return -1; 1278 } 1279 udelay (1); 1280 } 1281 return 0; 1282 } 1283 1284 /*-------------------------------------------------------------------------*/ 1285 1286 /* Start an OHCI controller, set the BUS operational 1287 * enable interrupts 1288 * connect the virtual root hub */ 1289 1290 static int hc_start (ohci_t * ohci) 1291 { 1292 __u32 mask; 1293 unsigned int fminterval; 1294 1295 ohci->disabled = 1; 1296 1297 /* Tell the controller where the control and bulk lists are 1298 * The lists are empty now. */ 1299 1300 writel (0, &ohci->regs->ed_controlhead); 1301 writel (0, &ohci->regs->ed_bulkhead); 1302 1303 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ 1304 1305 fminterval = 0x2edf; 1306 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); 1307 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1308 writel (fminterval, &ohci->regs->fminterval); 1309 writel (0x628, &ohci->regs->lsthresh); 1310 1311 /* start controller operations */ 1312 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1313 ohci->disabled = 0; 1314 writel (ohci->hc_control, &ohci->regs->control); 1315 1316 /* disable all interrupts */ 1317 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1318 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1319 OHCI_INTR_OC | OHCI_INTR_MIE); 1320 writel (mask, &ohci->regs->intrdisable); 1321 /* clear all interrupts */ 1322 mask &= ~OHCI_INTR_MIE; 1323 writel (mask, &ohci->regs->intrstatus); 1324 /* Choose the interrupts we care about now - but w/o MIE */ 1325 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1326 writel (mask, &ohci->regs->intrenable); 1327 1328 #ifdef OHCI_USE_NPS 1329 /* required for AMD-756 and some Mac platforms */ 1330 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, 1331 &ohci->regs->roothub.a); 1332 writel (RH_HS_LPSC, &ohci->regs->roothub.status); 1333 #endif /* OHCI_USE_NPS */ 1334 1335 /* POTPGT delay is bits 24-31, in 2 ms units. */ 1336 mdelay ((roothub_a (ohci) >> 23) & 0x1fe); 1337 1338 /* connect the virtual root hub */ 1339 ohci->rh.devnum = 0; 1340 1341 return 0; 1342 } 1343 1344 /*-------------------------------------------------------------------------*/ 1345 1346 /* an interrupt happens */ 1347 1348 static int 1349 hc_interrupt (void) 1350 { 1351 ohci_t *ohci = &gohci; 1352 struct ohci_regs *regs = ohci->regs; 1353 int ints; 1354 int stat = -1; 1355 1356 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { 1357 ints = OHCI_INTR_WDH; 1358 } else { 1359 ints = readl (®s->intrstatus); 1360 } 1361 1362 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ 1363 1364 if (ints & OHCI_INTR_RHSC) { 1365 got_rhsc = 1; 1366 } 1367 1368 if (ints & OHCI_INTR_UE) { 1369 ohci->disabled++; 1370 err ("OHCI Unrecoverable Error, controller usb-%s disabled", 1371 ohci->slot_name); 1372 /* e.g. due to PCI Master/Target Abort */ 1373 1374 #ifdef DEBUG 1375 ohci_dump (ohci, 1); 1376 #else 1377 mdelay(1); 1378 #endif 1379 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1380 /* Make some non-interrupt context restart the controller. */ 1381 /* Count and limit the retries though; either hardware or */ 1382 /* software errors can go forever... */ 1383 hc_reset (ohci); 1384 return -1; 1385 } 1386 1387 if (ints & OHCI_INTR_WDH) { 1388 mdelay(1); 1389 writel (OHCI_INTR_WDH, ®s->intrdisable); 1390 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); 1391 writel (OHCI_INTR_WDH, ®s->intrenable); 1392 } 1393 1394 if (ints & OHCI_INTR_SO) { 1395 dbg("USB Schedule overrun\n"); 1396 writel (OHCI_INTR_SO, ®s->intrenable); 1397 stat = -1; 1398 } 1399 1400 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1401 if (ints & OHCI_INTR_SF) { 1402 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; 1403 mdelay(1); 1404 writel (OHCI_INTR_SF, ®s->intrdisable); 1405 if (ohci->ed_rm_list[frame] != NULL) 1406 writel (OHCI_INTR_SF, ®s->intrenable); 1407 stat = 0xff; 1408 } 1409 1410 writel (ints, ®s->intrstatus); 1411 return stat; 1412 } 1413 1414 /*-------------------------------------------------------------------------*/ 1415 1416 /*-------------------------------------------------------------------------*/ 1417 1418 /* De-allocate all resources.. */ 1419 1420 static void hc_release_ohci (ohci_t *ohci) 1421 { 1422 dbg ("USB HC release ohci usb-%s", ohci->slot_name); 1423 1424 if (!ohci->disabled) 1425 hc_reset (ohci); 1426 } 1427 1428 /*-------------------------------------------------------------------------*/ 1429 1430 #define __read_32bit_c0_register(source, sel) \ 1431 ({ int __res; \ 1432 if (sel == 0) \ 1433 __asm__ __volatile__( \ 1434 "mfc0\t%0, " #source "\n\t" \ 1435 : "=r" (__res)); \ 1436 else \ 1437 __asm__ __volatile__( \ 1438 ".set\tmips32\n\t" \ 1439 "mfc0\t%0, " #source ", " #sel "\n\t" \ 1440 ".set\tmips0\n\t" \ 1441 : "=r" (__res)); \ 1442 __res; \ 1443 }) 1444 1445 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1446 1447 /* 1448 * low level initalisation routine, called from usb.c 1449 */ 1450 static char ohci_inited = 0; 1451 1452 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1453 { 1454 u32 pin_func; 1455 u32 sys_freqctrl, sys_clksrc; 1456 u32 prid = read_c0_prid(); 1457 1458 dbg("in usb_lowlevel_init\n"); 1459 1460 /* zero and disable FREQ2 */ 1461 sys_freqctrl = au_readl(SYS_FREQCTRL0); 1462 sys_freqctrl &= ~0xFFF00000; 1463 au_writel(sys_freqctrl, SYS_FREQCTRL0); 1464 1465 /* zero and disable USBH/USBD clocks */ 1466 sys_clksrc = au_readl(SYS_CLKSRC); 1467 sys_clksrc &= ~0x00007FE0; 1468 au_writel(sys_clksrc, SYS_CLKSRC); 1469 1470 sys_freqctrl = au_readl(SYS_FREQCTRL0); 1471 sys_freqctrl &= ~0xFFF00000; 1472 1473 sys_clksrc = au_readl(SYS_CLKSRC); 1474 sys_clksrc &= ~0x00007FE0; 1475 1476 switch (prid & 0x000000FF) { 1477 case 0x00: /* DA */ 1478 case 0x01: /* HA */ 1479 case 0x02: /* HB */ 1480 /* CPU core freq to 48MHz to slow it way down... */ 1481 au_writel(4, SYS_CPUPLL); 1482 1483 /* 1484 * Setup 48MHz FREQ2 from CPUPLL for USB Host 1485 */ 1486 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ 1487 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); 1488 au_writel(sys_freqctrl, SYS_FREQCTRL0); 1489 1490 /* CPU core freq to 384MHz */ 1491 au_writel(0x20, SYS_CPUPLL); 1492 1493 printf("Au1000: 48MHz OHCI workaround enabled\n"); 1494 break; 1495 1496 default: /* HC and newer */ 1497 /* FREQ2 = aux/2 = 48 MHz */ 1498 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); 1499 au_writel(sys_freqctrl, SYS_FREQCTRL0); 1500 break; 1501 } 1502 1503 /* 1504 * Route 48MHz FREQ2 into USB Host and/or Device 1505 */ 1506 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); 1507 au_writel(sys_clksrc, SYS_CLKSRC); 1508 1509 /* configure pins GPIO[14:9] as GPIO */ 1510 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); 1511 1512 au_writel(pin_func, SYS_PINFUNC); 1513 au_writel(0x2800, SYS_TRIOUTCLR); 1514 au_writel(0x0030, SYS_OUTPUTCLR); 1515 1516 dbg("OHCI board setup complete\n"); 1517 1518 /* enable host controller */ 1519 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); 1520 udelay(1000); 1521 au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); 1522 udelay(1000); 1523 1524 /* wait for reset complete (read register twice; see au1500 errata) */ 1525 while (au_readl(USB_HOST_CONFIG), 1526 !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) 1527 udelay(1000); 1528 1529 dbg("OHCI clock running\n"); 1530 1531 memset (&gohci, 0, sizeof (ohci_t)); 1532 memset (&urb_priv, 0, sizeof (urb_priv_t)); 1533 1534 /* align the storage */ 1535 if ((__u32)&ghcca[0] & 0xff) { 1536 err("HCCA not aligned!!"); 1537 return -1; 1538 } 1539 phcca = &ghcca[0]; 1540 info("aligned ghcca %p", phcca); 1541 memset(&ohci_dev, 0, sizeof(struct ohci_device)); 1542 if ((__u32)&ohci_dev.ed[0] & 0x7) { 1543 err("EDs not aligned!!"); 1544 return -1; 1545 } 1546 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); 1547 if ((__u32)gtd & 0x7) { 1548 err("TDs not aligned!!"); 1549 return -1; 1550 } 1551 ptd = gtd; 1552 gohci.hcca = phcca; 1553 memset (phcca, 0, sizeof (struct ohci_hcca)); 1554 1555 gohci.disabled = 1; 1556 gohci.sleeping = 0; 1557 gohci.irq = -1; 1558 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000); 1559 1560 gohci.flags = 0; 1561 gohci.slot_name = "au1x00"; 1562 1563 dbg("OHCI revision: 0x%08x\n" 1564 " RH: a: 0x%08x b: 0x%08x\n", 1565 readl(&gohci.regs->revision), 1566 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b)); 1567 1568 if (hc_reset (&gohci) < 0) 1569 goto errout; 1570 1571 /* FIXME this is a second HC reset; why?? */ 1572 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); 1573 mdelay (10); 1574 1575 if (hc_start (&gohci) < 0) 1576 goto errout; 1577 1578 #ifdef DEBUG 1579 ohci_dump (&gohci, 1); 1580 #else 1581 mdelay(1); 1582 #endif 1583 ohci_inited = 1; 1584 return 0; 1585 1586 errout: 1587 err("OHCI initialization error\n"); 1588 hc_release_ohci (&gohci); 1589 /* Initialization failed */ 1590 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); 1591 return -1; 1592 } 1593 1594 int usb_lowlevel_stop(int index) 1595 { 1596 /* this gets called really early - before the controller has */ 1597 /* even been initialized! */ 1598 if (!ohci_inited) 1599 return 0; 1600 /* TODO release any interrupts, etc. */ 1601 /* call hc_release_ohci() here ? */ 1602 hc_reset (&gohci); 1603 /* may not want to do this */ 1604 /* Disable clock */ 1605 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); 1606 return 0; 1607 } 1608 1609 #endif /* CONFIG_USB_OHCI */ 1610
