| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ia32/ |
| FlushCacheLine.c | 46 test edx, BIT19
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| FlushCacheLine.asm | 46 test edx, BIT19
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| SP804Timer.h | 52 #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcie.h | 75 #define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
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| PchRegsLpss.h | 64 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
149 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
236 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
323 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
415 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
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| /device/linaro/bootloader/edk2/Omap35xxPkg/PciEmulation/ |
| PciEmulation.c | 59 MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
60 MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 36 #undef BIT19
72 #define BIT19 0x00080000U
|
| meminit.c | 557 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
565 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
566 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
572 isbM32m(DDRPHY, (B0OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
573 isbM32m(DDRPHY, (B1OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
577 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
578 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2| (…)
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Library/BaseCacheMaintenanceLib/ |
| X86Cache.c | 142 if ((RegEdx & BIT19) == 0) {
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| Virtio095Net.h | 60 #define VIRTIO_NET_F_CTRL_VLAN BIT19 // control channel VLAN filtering
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
67 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
161 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/ |
| SataRegisters.h | 126 #define EFI_AHCI_PORT_CMD_MPSP BIT19
167 #define EFI_AHCI_PORT_SERR_BDE BIT19
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 97 #define BIT19 0x00080000
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530MMCHS.h | 67 #define CCCE_ENABLE BIT19
130 #define CIE_EN BIT19
145 #define CIE_SIGEN BIT19
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| Omap3530Dma.h | 66 #define DMA4_CSDP_DST_ENDIAN_BIG BIT19
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/ |
| OmapDmaLib.c | 93 RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 65 #define BIT19 0x00080000
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| AhciMode.h | 131 #define EFI_AHCI_PORT_CMD_MPSP BIT19
172 #define EFI_AHCI_PORT_SERR_BDE BIT19
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| XhciReg.h | 176 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
190 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 91 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
105 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| OpalAhciMode.h | 124 #define EFI_AHCI_PORT_CMD_MPSP BIT19
165 #define EFI_AHCI_PORT_SERR_BDE BIT19
|
| /external/epid-sdk/ext/ipp/sources/ippcp/ |
| cpinit.c | 144 #define BIT19 0x00080000
183 if( ecx_ & BIT19 ) mask |= ippCPUID_SSE41; // ecx[19] - Intel(R) Streaming SIMD Extensions 4.1 (Intel(R) SSE4.1) (formerly codenamed Penryn)
209 if( ebx_ & BIT19 ) mask |= ippCPUID_ADCOX; // eax[0x7] -->> ebx:: Bit 19: Intel(R) instructions ADOX/ADCX
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| AArch64.h | 65 #define ARM_HCR_TSC BIT19
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 102 #define MCI_STATUS_CMD_RXFIFOEMPTY BIT19
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| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 240 #define BIT19 0x00080000
|
