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Searched
refs:BIT3
(Results
1 - 25
of
158
) sorted by null
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/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/Include/Library/
CpldD03.h
22
#define BMC_I2C_STATUS
BIT3
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
SP804Timer.h
35
#define SP804_TIMER_CTRL_PRESCALE_MASK (
BIT3
|BIT2)
38
#define SP804_PRESCALE_DIV_256
BIT3
HdLcd.h
56
#define HDLCD_UNDERRUN
BIT3
/* No Data available while DATAEN active */
66
#define HDLCD_BURST_8
BIT3
73
#define HDLCD_DATA_HIGH
BIT3
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Usb.h
28
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
BIT3
38
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE
BIT3
Omap3530I2c.h
23
#define RRDY_IE
BIT3
30
#define RRDY
BIT3
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
53
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+
BIT3
+BIT2+BIT1+BIT0) // Master Target Address bits
68
#define I2C_REG_RAW_INTR_STAT_TX_OVER (
BIT3
) // Raw Interrupt Status Register TX Overflow signal status.
88
#define B_I2C_REG_TXFLR (
BIT3
+BIT2+BIT1+BIT0) // Transmit FIFO Level Register bits
90
#define B_I2C_REG_RXFLR (
BIT3
+BIT2+BIT1+BIT0) // Receive FIFO Level Register bits
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
52
#define USBPORTSC_PEDC
BIT3
// Port Enable / Disable Change
73
#define USBCMD_EGSM
BIT3
// Global Suspend Mode
85
#define USBSTS_HSE
BIT3
// Host System Error
93
#define USBTD_NAK
BIT3
// NAK is received
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsLpss.h
85
#define B_PCH_LPSS_DMAC_BAR_PF
BIT3
// Prefetchable
92
#define B_PCH_LPSS_DMAC_BAR1_PF
BIT3
// Prefetchable
121
#define B_PCH_LPSS_DMAC_PCS_NSS
BIT3
// No Soft Reset
170
#define B_PCH_LPSS_I2C_BAR_PF
BIT3
// Prefetchable
177
#define B_PCH_LPSS_I2C_BAR1_PF
BIT3
// Prefetchable
206
#define B_PCH_LPSS_I2C_PCS_NSS
BIT3
// No Soft Reset
257
#define B_PCH_LPSS_PWM_BAR_PF
BIT3
// Prefetchable
264
#define B_PCH_LPSS_PWM_BAR1_PF
BIT3
// Prefetchable
293
#define B_PCH_LPSS_PWM_PCS_NSS
BIT3
// No Soft Reset
344
#define B_PCH_LPSS_HSUART_BAR_PF
BIT3
// Prefetchable
[
all
...]
PchRegsSata.h
74
#define B_PCH_SATA_COMMAND_SCE
BIT3
// Special Cycle Enable
88
#define B_PCH_SATA_PCISTS_ITNS
BIT3
// Interrupt Status
93
#define B_PCH_SATA_PI_REGISTER_SNC
BIT3
// Secondary Mode Native Capable
144
#define B_PCH_SATA_ABAR_PF
BIT3
// Prefetchable
162
#define B_PCH_SATA_PMCS_NSFRST
BIT3
// No Soft Reset
196
#define B_PCH_SATA_PCS_PORT3_EN
BIT3
// Port 3 Enabled
205
#define B_PCH_SATA_PORT3_IMPLEMENTED
BIT3
// Port 3 Implemented
PchRegsSpi.h
50
#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 |
BIT3
) // Block / Sector Erase Size
82
#define B_PCH_SPI_OPTYPE1_MASK (
BIT3
| BIT2) // Opcode Type 1 Mask
110
#define B_PCH_SPI_BCR_SRC (
BIT3
| BIT2) // SPI Read Configuration (SRC)
PchRegsPcu.h
82
#define B_PCH_LPC_COMMAND_SCE
BIT3
// Special Cycle Enable
98
#define B_PCH_LPC_DEV_STS_INT_STS
BIT3
// Interrupt Status
146
#define B_PCH_LPC_PMC_BASE_PREF
BIT3
// Prefetchable
158
#define B_PCH_LPC_IO_BASE_PREF
BIT3
// Prefetchable
165
#define B_PCH_LPC_ILB_BASE_PREF
BIT3
// Prefetchable
172
#define B_PCH_LPC_SPI_BASE_PREF
BIT3
// Prefetchable
179
#define B_PCH_LPC_MPHY_BASE_PREF
BIT3
// Prefetchable
186
#define B_PCH_LPC_PUNIT_BASE_PREF
BIT3
// Prefetchable
205
#define B_PCH_LPC_FWH_BIOS_DEC_E70
BIT3
// 70-7F Enable
260
#define B_PCH_ILB_MC_DRTC
BIT3
// Disable RTC
[
all
...]
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
TpmPtp.h
180
#define PTP_FIFO_ACC_SEIZE
BIT3
214
#define PTP_FIFO_STS_EXPECT
BIT3
229
#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 |
BIT3
)
389
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 |
BIT3
| BIT4)
392
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (
BIT3
)
393
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 |
BIT3
)
415
#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT
BIT3
TpmTis.h
131
#define TIS_PC_ACC_SEIZE
BIT3
165
#define TIS_PC_STS_EXPECT
BIT3
/device/linaro/bootloader/edk2/SecurityPkg/Include/Guid/
TrEEPhysicalPresenceData.h
40
#define TREE_FLAG_RESET_TRACK
BIT3
PhysicalPresenceData.h
76
#define FLAG_RESET_TRACK
BIT3
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
28
#define CTRL4_FPGA_EXT_PHY_SEL
BIT3
37
#define CTRL5_USBOTG_RES_SEL
BIT3
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
IdeMode.h
63
#define BMIC_NREAD
BIT3
121
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR
BIT3
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
46
#define MCH_SMRAM_G_SMRAME
BIT3
53
#define MCH_ESMRAMC_SM_L2
BIT3
Virtio10.h
79
#define VSTAT_FEATURES_OK
BIT3
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
45
#define ISP1761_DC_INTERRUPT_SUSP
BIT3
71
#define ISP1761_ENDPOINT_TYPE_ENABLE
BIT3
81
#define ISP1761_CTRL_FUNCTION_VENDP
BIT3
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/
IdeData.h
116
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR
BIT3
122
#define BMIC_NREAD
BIT3
294
#define DTE0
BIT3
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
62
#define I2C_INTR_TX_OVER
BIT3
87
#define STAT_RFNE
BIT3
// RX FIFO is not empty
122
#define I2C_INTR_TX_OVER
BIT3
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
SataRegisters.h
93
#define EFI_AHCI_PORT_IS_SDBS
BIT3
119
#define EFI_AHCI_PORT_CMD_CLO
BIT3
136
#define EFI_AHCI_PORT_TFD_MASK (BIT7 |
BIT3
| BIT0)
138
#define EFI_AHCI_PORT_TFD_DRQ
BIT3
/device/linaro/bootloader/edk2/IntelFsp2Pkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 |
BIT3
| BIT2 | BIT1 | BIT0)
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 |
BIT3
| BIT2 | BIT1 | BIT0)
Completed in 2274 milliseconds
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