| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| StmStatusCode.h | 27 Success code have BIT31 clear.
28 All error codes have BIT31 set.
37 #define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)
38 #define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)
39 #define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)
40 #define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)
41 #define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)
42 #define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)
43 #define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)
44 #define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/ |
| SataRegisters.h | 24 #define EFI_AHCI_CAP_S64A BIT31
28 #define EFI_AHCI_GHC_ENABLE BIT31
106 #define EFI_AHCI_PORT_IS_CPDS BIT31
133 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 48 #undef BIT31
84 #define BIT31 0x80000000U
|
| meminit.c | 602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
606 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
607 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|(BIT11|BIT10|BIT9|BIT8)|BIT6|(BIT3|BIT2|BIT1|BIT0))); // Allow PUnit signals
626 isbM32m(DDRPHY, (COMPEN1CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT19|BIT17), ((BIT31|BIT30)|BIT19|BIT17|(BIT15|BIT14)));
640 isbM32m(DDRPHY, (COMPEN0CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (0), ((BIT31|BIT30)|BIT8)); // COMP
644 isbM32m(DDRPHY, (DQDRVPUCTLCH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP PU
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsSpi.h | 60 #define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable
66 #define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable
|
| PchRegsPcu.h | [all...] |
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| FdtPciPcdProducerLib.c | 38 #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
44 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Include/ |
| Hkadc.h | 25 #define WR1_WRITE_MODE BIT31
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| AhciMode.h | 22 #define EFI_AHCI_CAP_S64A BIT31
26 #define EFI_AHCI_GHC_ENABLE BIT31
114 #define EFI_AHCI_PORT_IS_CPDS BIT31
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioBlk.h | 83 #define VIRTIO_BLK_T_BARRIER BIT31
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 194 #define INSTS_SW_INT BIT31 // Software Interrupt occurred
288 #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter
320 #define E2P_EPC_BUSY BIT31
371 #define MAC_CSR_BUSY BIT31
379 #define TX_CMD_A_COMPLETION_INT BIT31
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QuarkNcSocId.h | 197 #define EnableIMRInt BIT31
199 #define EnableSMMInt BIT31
214 #define IMR_LOCK BIT31
380 #define B_QNC_LPC_SMBUS_BASE_EN (BIT31)
508 #define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI
521 #define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable
554 #define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/ |
| IntelQNCLib.c | 43 QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QNC_MSG_TMPM_REG_PMBA, (BIT31 | PcdGet16 (PcdPmbaIoBaseAddress)));
47 LpcPciCfg32 (R_QNC_LPC_SMBUS_BASE) = BIT31 | PcdGet16 (PcdSmbaIoBaseAddress);
48 LpcPciCfg32 (R_QNC_LPC_GBA_BASE) = BIT31 | PcdGet16 (PcdGbaIoBaseAddress);
49 LpcPciCfg32 (R_QNC_LPC_PM1BLK) = BIT31 | PcdGet16 (PcdPm1blkIoBaseAddress);
50 LpcPciCfg32 (R_QNC_LPC_GPE0BLK) = BIT31 | PcdGet16 (PcdGpe0blkIoBaseAddress);
51 LpcPciCfg32 (R_QNC_LPC_WDTBA) = BIT31 | PcdGet16 (PcdWdtbaIoBaseAddress);
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Include/Protocol/ |
| DisplayProtocol.h | 33 #define BROWSER_ERROR BIT31
84 #define STATEMENT_INVALID BIT31
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 85 #define BIT31 0x80000000
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| OpalAhciMode.h | 39 #define EFI_AHCI_GHC_ENABLE BIT31
107 #define EFI_AHCI_PORT_IS_CPDS BIT31
131 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/ |
| MonotonicCounter.c | 94 if ((((UINT32) mEfiMtc) ^ ((UINT32) *Count)) & BIT31) {
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 77 #define BIT31 0x80000000
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/ |
| IgdOpRegion.h | 97 #define FIELD_VALID_BIT BIT31
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| Ioh.h | 60 #define BIT31 0x80000000
217 #define B_IOH_MAC_AE BIT31
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 84 #define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT31 // Limited CPU support
178 #define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT31 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/Library/ |
| ArmGicLib.h | 269 #define ARM_GICD_IROUTER_IRM BIT31
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ |
| ArmVExpressSysConfig.c | 25 #define SYS_CFGCTRL_START BIT31
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ |
| ArmVExpressSysConfigRuntimeLib.c | 28 #define SYS_CFGCTRL_START BIT31
|
| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 252 #define BIT31 0x80000000
|
