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Searched
refs:BIT7
(Results
1 - 25
of
143
) sorted by null
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/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
I440FxPiix4.h
37
BIT10 | BIT9 | BIT8 |
BIT7
| BIT6)
Q35MchIch9.h
49
#define MCH_ESMRAMC_H_SMRAME
BIT7
80
BIT10 | BIT9 | BIT8 |
BIT7
)
83
#define ICH9_ACPI_CNTL_ACPI_EN
BIT7
Virtio095Net.h
48
#define VIRTIO_NET_F_GUEST_TSO4
BIT7
// guest can receive TSOv4
89
#define VIRTIO_NET_HDR_GSO_ECN
BIT7
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
Fdc.h
47
#define MSR_RQM
BIT7
// Request For Master
55
#define DIR_DCL
BIT7
// Disk change line
74
#define CMD_MT
BIT7
97
#define STS0_IC (
BIT7
| BIT6) // Interrupt Code
110
#define STS1_EN
BIT7
// End of Cylinder
126
//
BIT7
is unused
141
//
BIT7
is unused
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
78
#define TCR_PAD_EN
BIT7
97
#define EPHSR_TX_DEFR
BIT7
123
#define RPCR_LS2A
BIT7
142
#define CTR_LE_ENABLE
BIT7
167
#define ARR_FAILED
BIT7
171
#define FIFO_TEMPTY
BIT7
189
#define IST_MD
BIT7
200
#define RCV_RCV_DISCRD
BIT7
245
#define PHYCR_COLL_TEST
BIT7
// Collision test enable
272
#define PHYANA_100BASETX
BIT7
// Advertise 100BASETX capability
[
all
...]
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
SP804Timer.h
41
#define SP804_TIMER_CTRL_ENABLE
BIT7
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
49
#define ISP1761_DC_INTERRUPT_VBUS
BIT7
59
#define ISP1761_ADDRESS_DEVEN
BIT7
63
#define ISP1761_MODE_CLKAON
BIT7
103
#define ISP1761_OTG_STATUS_B_SESS_END
BIT7
/device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/
SmmStmSupport.c
25
#define IA32_PG_PS
BIT7
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
41
#define CTRL5_PICOPHY_VDATSRCEND
BIT7
62
#define RST0_USBOTG_32K
BIT7
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
TpmTis.h
116
#define TIS_PC_VALID
BIT7
148
#define TIS_PC_STS_VALID
BIT7
TpmPtp.h
165
#define PTP_FIFO_VALID
BIT7
197
#define PTP_FIFO_STS_VALID
BIT7
380
#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS
BIT7
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/
ResetSystemLib.c
82
if ((Data8 &
BIT7
) ==
BIT7
) {
83
while ((Data8 &
BIT7
) ==
BIT7
) {
89
while ((Data8 &
BIT7
) == 0) {
94
while ((Data8 &
BIT7
) ==
BIT7
) {
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/
UsbMass.h
44
#define USB_IS_IN_ENDPOINT(EndPointAddr) (((EndPointAddr) &
BIT7
) ==
BIT7
)
45
#define USB_IS_OUT_ENDPOINT(EndPointAddr) (((EndPointAddr) &
BIT7
) == 0)
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsSmbus.h
57
#define B_PCH_SMBUS_PCICMD_WCC
BIT7
// Wait Cycle Control - reserved as '0'
78
#define B_PCH_SMBUS_BYTE_DONE_STS
BIT7
// Byte Done Status
89
#define B_PCH_SMBUS_PEC_EN
BIT7
// Packet Error Checking Enable
PchRegsPcu.h
78
#define B_PCH_LPC_COMMAND_WCC
BIT7
// Wait Cycle Control
95
#define B_PCH_LPC_DEV_STS_FB2B
BIT7
// Fast Back to Back Capable
129
#define B_PCH_LPC_HEADTYP_MFD
BIT7
// Multi-function Device
203
#define B_PCH_LPC_FWH_BIOS_DEC_LFE
BIT7
// Legacy F Segment Enable
276
#define B_PCH_ILB_PIRQX_ROUT_IRQEN
BIT7
// Interrupt Routing Enable
291
#define B_PCH_ILB_SERIRQ_CNT_SIRQMD
BIT7
// Mode
456
#define B_PCH_ILB_IRQE_IRQ4TO7EN (
BIT7
| BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable
[
all
...]
PchRegsSata.h
70
#define B_PCH_SATA_COMMAND_WCC
BIT7
// Wait Cycle Enable
112
#define B_PCH_SATA_HTYPE_MFD
BIT7
// Multi-function Device
178
#define B_PCH_SATA_MAP_SMS_MASK (
BIT7
| BIT6) // SATA Mode Select
/device/linaro/bootloader/edk2/IntelFsp2Pkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (
BIT7
| BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (
BIT7
| BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Uart.h
36
#define UART_LCR_DIV_EN_ENABLE
BIT7
Omap3530Dma.h
86
#define DMA4_CCR_ENABLE
BIT7
116
#define DMA4_CSR_PKT
BIT7
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
62
// and if more, check whether the
bit7
of PORTSC is always 1.
77
#define USBCMD_MAXP
BIT7
// Max Packet (0 = 32, 1 = 64)
89
#define USBTD_ACTIVE
BIT7
// TD is still active
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
24
#undef
BIT7
60
#define
BIT7
0x00000080U
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
SataRegisters.h
97
#define EFI_AHCI_PORT_IS_DIS
BIT7
136
#define EFI_AHCI_PORT_TFD_MASK (
BIT7
| BIT3 | BIT0)
137
#define EFI_AHCI_PORT_TFD_BSY
BIT7
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
76
#define MCI_POWER_ROD
BIT7
90
#define MCI_STATUS_CMD_SENT
BIT7
143
#define MCI_CPSM_LONG_RESPONSE
BIT7
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/
UfsPassThru.c
196
UfsLun =
BIT7
| (((UINT8*)&Lun)[1] & 0xFF);
286
if ((UfsLun &
BIT7
) ==
BIT7
) {
288
((UINT8*)Lun)[1] = UfsLun & ~
BIT7
;
301
UfsLun =
BIT7
| (((UINT8*)Lun)[1] & 0xFF);
333
if ((UfsLun &
BIT7
) ==
BIT7
) {
335
((UINT8*)Lun)[1] = UfsLun & ~
BIT7
;
400
UfsLun =
BIT7
| (((UINT8*)&Lun)[1] & 0xFF);
514
if ((UfsLun &
BIT7
) == BIT7) {
[
all
...]
Completed in 265 milliseconds
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