1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <i2c.h> 9 #include <netdev.h> 10 #include <linux/compiler.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <asm/immap_85xx.h> 14 #include <asm/fsl_law.h> 15 #include <asm/fsl_serdes.h> 16 #include <asm/fsl_liodn.h> 17 #include <fm_eth.h> 18 #include "t102xrdb.h" 19 #ifdef CONFIG_TARGET_T1024RDB 20 #include "cpld.h" 21 #elif defined(CONFIG_TARGET_T1023RDB) 22 #include <i2c.h> 23 #include <mmc.h> 24 #endif 25 #include "../common/sleep.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #ifdef CONFIG_TARGET_T1023RDB 30 enum { 31 GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */ 32 GPIO1_EMMC_SEL, 33 GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */ 34 GPIO3_BRD_VER_MASK = 0x0c000000, 35 GPIO3_OFFSET = 0x2000, 36 I2C_GET_BANK, 37 I2C_SET_BANK0, 38 I2C_SET_BANK4, 39 }; 40 #endif 41 42 int checkboard(void) 43 { 44 struct cpu_type *cpu = gd->arch.cpu; 45 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; 46 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 47 u32 srds_s1; 48 49 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 50 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 51 52 printf("Board: %sRDB, ", cpu->name); 53 #if defined(CONFIG_TARGET_T1024RDB) 54 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", 55 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); 56 #elif defined(CONFIG_TARGET_T1023RDB) 57 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B'); 58 #endif 59 printf("boot from "); 60 61 #ifdef CONFIG_SDCARD 62 puts("SD/MMC\n"); 63 #elif CONFIG_SPIFLASH 64 puts("SPI\n"); 65 #elif defined(CONFIG_TARGET_T1024RDB) 66 u8 reg; 67 68 reg = CPLD_READ(flash_csr); 69 70 if (reg & CPLD_BOOT_SEL) { 71 puts("NAND\n"); 72 } else { 73 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); 74 printf("NOR vBank%d\n", reg); 75 } 76 #elif defined(CONFIG_TARGET_T1023RDB) 77 #ifdef CONFIG_NAND 78 puts("NAND\n"); 79 #else 80 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK)); 81 #endif 82 #endif 83 84 puts("SERDES Reference Clocks:\n"); 85 if (srds_s1 == 0x95) 86 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); 87 else 88 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]); 89 90 return 0; 91 } 92 93 #ifdef CONFIG_TARGET_T1024RDB 94 static void board_mux_lane(void) 95 { 96 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 97 u32 srds_prtcl_s1; 98 u8 reg = CPLD_READ(misc_ctl_status); 99 100 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 101 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 102 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 103 104 if (srds_prtcl_s1 == 0x95) { 105 /* Route Lane B to PCIE */ 106 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); 107 } else { 108 /* Route Lane B to SGMII */ 109 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); 110 } 111 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); 112 } 113 #endif 114 115 int board_early_init_f(void) 116 { 117 #if defined(CONFIG_DEEP_SLEEP) 118 if (is_warm_boot()) 119 fsl_dp_disable_console(); 120 #endif 121 122 return 0; 123 } 124 125 int board_early_init_r(void) 126 { 127 #ifdef CONFIG_SYS_FLASH_BASE 128 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 129 int flash_esel = find_tlb_idx((void *)flashbase, 1); 130 /* 131 * Remap Boot flash region to caching-inhibited 132 * so that flash can be erased properly. 133 */ 134 135 /* Flush d-cache and invalidate i-cache of any FLASH data */ 136 flush_dcache(); 137 invalidate_icache(); 138 if (flash_esel == -1) { 139 /* very unlikely unless something is messed up */ 140 puts("Error: Could not find TLB for FLASH BASE\n"); 141 flash_esel = 2; /* give our best effort to continue */ 142 } else { 143 /* invalidate existing TLB entry for flash + promjet */ 144 disable_tlb(flash_esel); 145 } 146 147 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 148 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 149 0, flash_esel, BOOKE_PAGESZ_256M, 1); 150 #endif 151 152 #ifdef CONFIG_TARGET_T1024RDB 153 board_mux_lane(); 154 #endif 155 156 return 0; 157 } 158 159 unsigned long get_board_sys_clk(void) 160 { 161 return CONFIG_SYS_CLK_FREQ; 162 } 163 164 unsigned long get_board_ddr_clk(void) 165 { 166 return CONFIG_DDR_CLK_FREQ; 167 } 168 169 #ifdef CONFIG_TARGET_T1024RDB 170 void board_reset(void) 171 { 172 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); 173 } 174 #endif 175 176 int misc_init_r(void) 177 { 178 return 0; 179 } 180 181 int ft_board_setup(void *blob, bd_t *bd) 182 { 183 phys_addr_t base; 184 phys_size_t size; 185 186 ft_cpu_setup(blob, bd); 187 188 base = env_get_bootm_low(); 189 size = env_get_bootm_size(); 190 191 fdt_fixup_memory(blob, (u64)base, (u64)size); 192 193 #ifdef CONFIG_PCI 194 pci_of_setup(blob, bd); 195 #endif 196 197 fdt_fixup_liodn(blob); 198 fsl_fdt_fixup_dr_usb(blob, bd); 199 200 #ifdef CONFIG_SYS_DPAA_FMAN 201 fdt_fixup_fman_ethernet(blob); 202 fdt_fixup_board_enet(blob); 203 #endif 204 205 #ifdef CONFIG_TARGET_T1023RDB 206 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0) 207 fdt_enable_nor(blob); 208 #endif 209 210 return 0; 211 } 212 213 #ifdef CONFIG_TARGET_T1023RDB 214 /* Enable NOR flash for RevC */ 215 static void fdt_enable_nor(void *blob) 216 { 217 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash"); 218 219 if (nodeoff >= 0) 220 fdt_status_okay(blob, nodeoff); 221 else 222 printf("WARNING unable to set status for NOR\n"); 223 } 224 225 int board_mmc_getcd(struct mmc *mmc) 226 { 227 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 228 u32 val = in_be32(&pgpio->gpdat); 229 230 /* GPIO1_14, 0: eMMC, 1: SD/MMC */ 231 val &= GPIO1_SD_SEL; 232 233 return val ? -1 : 1; 234 } 235 236 int board_mmc_getwp(struct mmc *mmc) 237 { 238 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 239 u32 val = in_be32(&pgpio->gpdat); 240 241 val &= GPIO1_SD_SEL; 242 243 return val ? -1 : 0; 244 } 245 246 static u32 t1023rdb_ctrl(u32 ctrl_type) 247 { 248 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 249 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 250 u32 val, orig_bus = i2c_get_bus_num(); 251 u8 tmp; 252 253 switch (ctrl_type) { 254 case GPIO1_SD_SEL: 255 val = in_be32(&pgpio->gpdat); 256 val |= GPIO1_SD_SEL; 257 out_be32(&pgpio->gpdat, val); 258 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); 259 break; 260 case GPIO1_EMMC_SEL: 261 val = in_be32(&pgpio->gpdat); 262 val &= ~GPIO1_SD_SEL; 263 out_be32(&pgpio->gpdat, val); 264 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); 265 break; 266 case GPIO3_GET_VERSION: 267 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR 268 + GPIO3_OFFSET); 269 val = in_be32(&pgpio->gpdat); 270 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; 271 if (val == 0x3) /* GPIO3_4/5 not used on RevB */ 272 val = 0; 273 return val; 274 case I2C_GET_BANK: 275 i2c_set_bus_num(I2C_PCA6408_BUS_NUM); 276 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); 277 tmp &= 0x7; 278 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); 279 i2c_set_bus_num(orig_bus); 280 return tmp; 281 case I2C_SET_BANK0: 282 i2c_set_bus_num(I2C_PCA6408_BUS_NUM); 283 tmp = 0x0; 284 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); 285 tmp = 0xf8; 286 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); 287 /* asserting HRESET_REQ */ 288 out_be32(&gur->rstcr, 0x2); 289 break; 290 case I2C_SET_BANK4: 291 i2c_set_bus_num(I2C_PCA6408_BUS_NUM); 292 tmp = 0x1; 293 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); 294 tmp = 0xf8; 295 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); 296 out_be32(&gur->rstcr, 0x2); 297 break; 298 default: 299 break; 300 } 301 return 0; 302 } 303 304 static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 305 char * const argv[]) 306 { 307 if (argc < 2) 308 return CMD_RET_USAGE; 309 if (!strcmp(argv[1], "bank0")) 310 t1023rdb_ctrl(I2C_SET_BANK0); 311 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank")) 312 t1023rdb_ctrl(I2C_SET_BANK4); 313 else if (!strcmp(argv[1], "sd")) 314 t1023rdb_ctrl(GPIO1_SD_SEL); 315 else if (!strcmp(argv[1], "emmc")) 316 t1023rdb_ctrl(GPIO1_EMMC_SEL); 317 else 318 return CMD_RET_USAGE; 319 return 0; 320 } 321 322 U_BOOT_CMD( 323 switch, 2, 0, switch_cmd, 324 "for bank0/bank4/sd/emmc switch control in runtime", 325 "command (e.g. switch bank4)" 326 ); 327 #endif 328
