| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/ |
| PciHostResource.h | 36 UINTN IoBase;
|
| PciHostBridge.c | 164 PrivateData->Aperture.IoBase = PcdGet16 (PcdPciHostBridgeIoBase);
411 if (RootBridgeInstance->Aperture.IoBase < RootBridgeInstance->Aperture.IoLimit) {
418 BaseAddress = RootBridgeInstance->Aperture.IoBase;
[all...] |
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciHostBridgeLib/ |
| FdtPciHostBridgeLib.c | 88 OUT UINT64 *IoBase,
114 *IoBase = 0;
209 *IoBase = SwapBytes64 (Record->ChildBase);
211 IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
267 __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,
289 UINT64 IoBase, IoSize;
302 Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,
328 mRootBridge.Io.Base = IoBase;
329 mRootBridge.Io.Limit = IoBase + IoSize - 1;
|
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| FdtPciPcdProducerLib.c | 58 UINT64 IoBase;
78 IoBase = SwapBytes64 (Record->ChildBase);
79 *IoTranslation = SwapBytes64 (Record->CpuBase) - IoBase;
|
| /device/linaro/bootloader/edk2/CorebootModulePkg/Library/BaseSerialPortLib16550/ |
| BaseSerialPortLib16550.c | 197 UINT32 IoBase;
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
276 IoBase = IoBase >> 4;
278 IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
284 if (IoLimit < IoBase) {
291 if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit)
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Library/BaseSerialPortLib16550/ |
| BaseSerialPortLib16550.c | 197 UINT32 IoBase;
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
276 IoBase = IoBase >> 4;
278 IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
284 if (IoLimit < IoBase) {
291 if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
[all...] |
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/ |
| PcatPciRootBridge.c | 105 PrivateData->IoBase = 0xffffffff;
251 Value = PciConfigurationHeader.Bridge.IoBase & 0x0f;
252 Base = ((UINT32)PciConfigurationHeader.Bridge.IoBase & 0xf0) << 8;
259 if (PrivateData->IoBase > Base) {
260 PrivateData->IoBase = Base;
434 PrivateData->IoBase = 0;
572 if (PrivateData->IoLimit >= PrivateData->IoBase) {
651 if (PrivateData->IoLimit >= PrivateData->IoBase) {
656 Configuration->AddrRangeMin = PrivateData->IoBase;
866 if (PrivateData->IoBase > Base) {
[all...] |
| PcatPciRootBridge.h | 66 UINT64 IoBase; // Offsets host to bus io addr.
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| MemoryCallback.c | 150 UINT32 IoBase;
216 IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
220 IoBase,
223 DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
|
| PchInitPeim.c | 619 UINT32 IoBase;
655 PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS;
712 IoBase = MmioRead32 (MmPciAddress (0,
718 MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/ |
| PciEnumerator.h | 270 @param IoBase Output of I/O resource base address.
280 OUT UINT64 *IoBase,
320 @param IoBase Output for base address of I/O type resource.
333 OUT UINT64 *IoBase,
|
| PciEnumerator.c | [all...] |
| PciLib.c | 370 UINT64 IoBase;
787 &IoBase,
819 IoBase,
855 IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/ |
| PchPlatformPolicy.h | 151 UINT32 IoBase; // IO Base Address.
|
| /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/ |
| PciDeviceSupport.c | 494 if ((((PciData.Bridge.IoBase & 0xF) == 0) &&
495 (PciData.Bridge.IoBase != 0 || PciData.Bridge.IoLimit != 0)) ||
496 (((PciData.Bridge.IoBase & 0xF) == 1) &&
497 ((PciData.Bridge.IoBase & 0xF0) != 0 || (PciData.Bridge.IoLimit & 0xF0) != 0 || PciData.Bridge.IoBaseUpper16 != 0 || PciData.Bridge.IoLimitUpper16 != 0))) {
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/ |
| Platform.c | 224 UINT32 IoBase = 0;
233 IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
235 MmioConf0 = IoBase + SSUSOffset + PConf0Offset;
236 MmioPadval = IoBase + SSUSOffset + PValueOffset;
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| PciRootBridgeIo.c | [all...] |
| PciHostBridge.h | 468 UINT64 IoBase;
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/PciHostBridgeLib/ |
| XenSupport.c | 279 Value = Pci.Bridge.IoBase & 0x0f;
280 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| Lan91xDxe.c | 72 UINTN IoBase; // I/O Base Address
223 MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank);
243 return MmioRead16 (LanDriver->IoBase + Offset);
262 return MmioWrite16 (LanDriver->IoBase + Offset, Value);
280 return MmioRead8 (LanDriver->IoBase + Offset);
299 return MmioWrite8 (LanDriver->IoBase + Offset, Value);
451 Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
900 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
910 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
[all...] |
| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/ |
| PciHostBridgeSupport.c | 405 Value = Pci.Bridge.IoBase & 0x0f;
406 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/ |
| PcatIo.c | 80 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
183 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Library/ |
| PlatformPciLib.h | 198 UINT64 IoBase;
|
| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/ |
| pci22.h | 71 UINT8 IoBase;
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ |
| pci22.h | 78 UINT8 IoBase;
|
