Home | History | Annotate | Download | only in Library 
      1 /** @file
      2 *
      3 *  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
      4 *  Copyright (c) 2016, Linaro Limited. All rights reserved.
      5 *
      6 *  This program and the accompanying materials
      7 *  are licensed and made available under the terms and conditions of the BSD License
      8 *  which accompanies this distribution.  The full text of the license may be found at
      9 *  http://opensource.org/licenses/bsd-license.php
     10 *
     11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     13 *
     14 **/
     15 
     16 #ifndef _PLATFORM_PCI_LIB_H_
     17 #define _PLATFORM_PCI_LIB_H_
     18 
     19 #define PCIE_MAX_HOSTBRIDGE      2
     20 #define PCIE_MAX_ROOTBRIDGE      8
     21 //The extern pcie addresses will be initialized by oemmisclib
     22 extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
     23 extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
     24 extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
     25 extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
     26 
     27 
     28 #define PCI_HB0RB0_PCI_BASE        FixedPcdGet64(PciHb0Rb0Base)
     29 #define PCI_HB0RB1_PCI_BASE        FixedPcdGet64(PciHb0Rb1Base)
     30 #define PCI_HB0RB2_PCI_BASE        FixedPcdGet64(PciHb0Rb2Base)
     31 #define PCI_HB0RB3_PCI_BASE        FixedPcdGet64(PciHb0Rb3Base)
     32 #define PCI_HB0RB4_PCI_BASE        FixedPcdGet64(PciHb0Rb4Base)
     33 #define PCI_HB0RB5_PCI_BASE        FixedPcdGet64(PciHb0Rb5Base)
     34 #define PCI_HB0RB6_PCI_BASE        FixedPcdGet64(PciHb0Rb6Base)
     35 #define PCI_HB0RB7_PCI_BASE        FixedPcdGet64(PciHb0Rb7Base)
     36 
     37 #define PCI_HB1RB0_PCI_BASE        FixedPcdGet64(PciHb1Rb0Base)
     38 #define PCI_HB1RB1_PCI_BASE        FixedPcdGet64(PciHb1Rb1Base)
     39 #define PCI_HB1RB2_PCI_BASE        FixedPcdGet64(PciHb1Rb2Base)
     40 #define PCI_HB1RB3_PCI_BASE        FixedPcdGet64(PciHb1Rb3Base)
     41 #define PCI_HB1RB4_PCI_BASE        FixedPcdGet64(PciHb1Rb4Base)
     42 #define PCI_HB1RB5_PCI_BASE        FixedPcdGet64(PciHb1Rb5Base)
     43 #define PCI_HB1RB6_PCI_BASE        FixedPcdGet64(PciHb1Rb6Base)
     44 #define PCI_HB1RB7_PCI_BASE        FixedPcdGet64(PciHb1Rb7Base)
     45 
     46 #define PCI_HB0RB0_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress)
     47 #define PCI_HB0RB0_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize)
     48 #define PCI_HB0RB1_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceBaseAddress)
     49 #define PCI_HB0RB1_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceSize)
     50 #define PCI_HB0RB2_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceBaseAddress)
     51 #define PCI_HB0RB2_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize)
     52 #define PCI_HB0RB3_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress)
     53 #define PCI_HB0RB3_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize)
     54 #define PCI_HB0RB4_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress)
     55 #define PCI_HB0RB4_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize)
     56 #define PCI_HB0RB5_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress)
     57 #define PCI_HB0RB5_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize)
     58 #define PCI_HB0RB6_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress)
     59 #define PCI_HB0RB6_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize)
     60 #define PCI_HB0RB7_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress)
     61 #define PCI_HB0RB7_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize)
     62 
     63 #define PCI_HB1RB0_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress)
     64 #define PCI_HB1RB0_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize)
     65 #define PCI_HB1RB1_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress)
     66 #define PCI_HB1RB1_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize)
     67 #define PCI_HB1RB2_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress)
     68 #define PCI_HB1RB2_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize)
     69 #define PCI_HB1RB3_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress)
     70 #define PCI_HB1RB3_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize)
     71 #define PCI_HB1RB4_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress)
     72 #define PCI_HB1RB4_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize)
     73 #define PCI_HB1RB5_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress)
     74 #define PCI_HB1RB5_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize)
     75 #define PCI_HB1RB6_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress)
     76 #define PCI_HB1RB6_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize)
     77 #define PCI_HB1RB7_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress)
     78 #define PCI_HB1RB7_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize)
     79 
     80 #define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress))
     81 #define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize))
     82 #define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress))
     83 #define PCI_HB0RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb1PciRegionSize))
     84 #define PCI_HB0RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb2PciRegionBaseAddress))
     85 #define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize))
     86 #define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress))
     87 #define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize))
     88 #define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress))
     89 #define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize))
     90 #define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress))
     91 #define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize))
     92 #define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress))
     93 #define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize))
     94 #define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress))
     95 #define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize))
     96 
     97 #define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress))
     98 #define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize))
     99 #define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress))
    100 #define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize))
    101 #define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress))
    102 #define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize))
    103 #define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress))
    104 #define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize))
    105 #define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress))
    106 #define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize))
    107 #define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress))
    108 #define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize))
    109 #define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress))
    110 #define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize))
    111 #define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress))
    112 #define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize))
    113 
    114 
    115 #define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase))
    116 #define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase))
    117 #define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase))
    118 #define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase))
    119 #define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase))
    120 #define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase))
    121 #define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase))
    122 #define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase))
    123 
    124 #define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase))
    125 #define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase))
    126 #define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase))
    127 #define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase))
    128 #define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase))
    129 #define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase))
    130 #define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase))
    131 #define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase))
    132 
    133 
    134 #define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase))
    135 #define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase))
    136 #define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase))
    137 #define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase))
    138 #define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase))
    139 #define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase))
    140 #define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase))
    141 #define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase))
    142 
    143 #define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase))
    144 #define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase))
    145 #define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase))
    146 #define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase))
    147 #define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase))
    148 #define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase))
    149 #define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase))
    150 #define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase))
    151 
    152 
    153 
    154 #define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase))
    155 #define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase))
    156 #define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase))
    157 #define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase))
    158 #define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase))
    159 #define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase))
    160 #define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase))
    161 #define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase))
    162 
    163 #define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase))
    164 #define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase))
    165 #define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase))
    166 #define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase))
    167 #define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase))
    168 #define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase))
    169 #define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase))
    170 #define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase))
    171 
    172 #define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize))
    173 #define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize))
    174 #define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize))
    175 #define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize))
    176 #define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize))
    177 #define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize))
    178 #define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize))
    179 #define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize))
    180 
    181 #define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize))
    182 #define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize))
    183 #define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize))
    184 #define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize))
    185 #define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize))
    186 #define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize))
    187 #define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize))
    188 #define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize))
    189 
    190 
    191 
    192 typedef struct {
    193   UINT64          Ecam;
    194   UINT64          BusBase;
    195   UINT64          BusLimit;
    196   UINT64          MemBase;
    197   UINT64          MemLimit;
    198   UINT64          IoBase;
    199   UINT64          IoLimit;
    200   UINT64          CpuMemRegionBase;
    201   UINT64          CpuIoRegionBase;
    202   UINT64          RbPciBar;
    203   UINT64          PciRegionBase;
    204   UINT64          PciRegionLimit;
    205 } PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
    206 
    207 extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
    208 #endif
    209 
    210