| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| suspend.h | 12 #define MHz (1000 * KHz)
13 #define GHz (1000 * MHz)
|
| suspend.c | 683 (refdiv * postdiv1 * postdiv2)) * MHz;
|
| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| cru_rk3328.h | 47 #define MHz 1000000
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
56 #define PCLK_DBG_HZ (300 * MHz)
62 #define PWM_CLOCK_HZ (74 * MHz)
|
| cru_rk3399.h | 69 #define MHz 1000000
71 #define OSC_HZ (24*MHz)
72 #define APLL_HZ (600*MHz)
73 #define GPLL_HZ (594*MHz)
74 #define CPLL_HZ (384*MHz)
75 #define PPLL_HZ (676*MHz)
77 #define PMU_PCLK_HZ (48*MHz)
79 #define ACLKM_CORE_HZ (300*MHz)
80 #define ATCLK_CORE_HZ (300*MHz)
81 #define PCLK_DBG_HZ (100*MHz)
[all...] |
| cru_rk3128.h | 11 #define MHz 1000000
12 #define OSC_HZ (24 * MHz)
14 #define APLL_HZ (600 * MHz)
15 #define GPLL_HZ (594 * MHz)
|
| cru_rk322x.h | 10 #define MHz 1000000
11 #define OSC_HZ (24 * MHz)
13 #define APLL_HZ (600 * MHz)
14 #define GPLL_HZ (594 * MHz)
|
| /external/linux-kselftest/tools/testing/selftests/intel_pstate/ |
| run.sh | 6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
102 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
105 echo "The marketing frequency of the cpu is $mkt_freq MHz"
[all...] |
| /external/u-boot/board/samsung/smdkc100/ |
| lowlevel_init.S | 91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
|
| /external/u-boot/drivers/video/rockchip/ |
| rk3288_mipi.c | 26 #define MHz 1000000
91 priv->ref_clk = 24 * MHz;
96 priv->txesc_clk = 20 * MHz;
|
| rk_mipi.c | 233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
244 if (ddr_clk / (MHz) >= freq_rang[i][0])
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
261 max_prediv = (refclk / (5 * MHz));
262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
|
| rk3399_mipi.c | 83 priv->ref_clk = 24 * MHz;
88 priv->txesc_clk = 20 * MHz;
|
| /external/u-boot/drivers/clk/rockchip/ |
| clk_rk3368.c | 205 const ulong MHz = 1000000;
212 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
285 const ulong MHz = 1000000;
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
293 case 1200*MHz:
296 case 1332*MHz:
299 case 1600*MHz:
|
| clk_rk3399.c | 56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
264 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
265 #define VCO_MIN_KHZ (800 * (MHz / KHz))
266 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
267 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
286 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
389 if (best_diff_khz > 4 * (MHz/KHz)) {
391 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
621 int aclk_vop = 198*MHz;
[all...] |
| clk_rk3328.c | 40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
179 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
180 #define VCO_MIN_KHZ (800 * (MHz / KHz))
181 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
182 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
201 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
489 /* use 24MHz source for 400KHz clock */
|
| clk_rk322x.c | 321 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
323 case 400*MHz:
327 case 600*MHz:
331 case 800*MHz:
|
| /external/u-boot/board/samsung/goni/ |
| lowlevel_init.S | 257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
320 ldr r1, =0x80C80601 @ 800MHz
323 ldr r1, =0x829B0C01 @ 667MHz
326 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
329 ldr r1, =0x806C0603 @ 54MHz
342 /* XCLKOUT = XUSBXTI 24MHz */
|
| /external/u-boot/drivers/ram/rockchip/ |
| dmc-rk3368.c | 354 * 5us will ensure this for a DRAM clock as low as 200MHz).
433 const ulong MHz = 1000000;
434 return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
444 const ulong MHz = 1000000;
445 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
452 const ulong MHz = 1000000;
463 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
464 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
471 if (freq <= (400 * MHz)) {
474 } else if (freq <= (533 * MHz)) {
[all...] |
| sdram_rk322x.c | 691 sdram_params->base.ddr_freq * MHz * 2);
|
| sdram_rk3399.c | [all...] |
| /external/u-boot/board/imgtec/xilfpga/ |
| README | 19 - 50MHz clock speed
|
| /external/u-boot/drivers/video/ |
| Kconfig | 333 int "SSD2828 TX_CLK frequency (in MHz)"
338 anything in the 8MHz-30MHz range and the exact value should be
|
| /external/u-boot/drivers/i2c/ |
| Kconfig | 387 _ Fast-mode Plus (up to 1 MHz)
|
| /external/u-boot/doc/ |
| README.x86 | [all...] |
