| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegAllocGreedy.cpp | 446 SmallVectorImpl<LiveInterval*> &NewVRegs) {
464 evictInterference(VirtReg, Hint, NewVRegs);
478 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
583 SmallVectorImpl<LiveInterval*> &NewVRegs) {
604 NewVRegs.push_back(Intf);
615 SmallVectorImpl<LiveInterval*> &NewVRegs,
658 evictInterference(VirtReg, BestPhys, NewVRegs);
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 535 StartIdx = NewVRegs.size();
538 NewVRegs.push_back(0);
543 return make_range(&NewVRegs[StartIdx], End);
554 assert((NewVRegs.size() == StartIdx + NumVal ||
555 NewVRegs.size() > StartIdx + NumVal) &&
556 "NewVRegs too small to contain all the partial mapping");
557 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
558 : &NewVRegs[StartIdx + NumVal];
586 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &
[all...] |
| RegBankSelect.cpp | 109 const iterator_range<SmallVectorImpl<unsigned>::const_iterator> &NewVRegs) {
112 assert(NewVRegs.begin() != NewVRegs.end() && "We should not have to repair");
117 unsigned Dst = *NewVRegs.begin();
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 624 StartIdx = NewVRegs.size();
627 NewVRegs.push_back(0);
632 return make_range(&NewVRegs[StartIdx], End);
643 assert((NewVRegs.size() == StartIdx + NumVal ||
644 NewVRegs.size() > StartIdx + NumVal) &&
645 "NewVRegs too small to contain all the partial mapping");
646 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
647 : &NewVRegs[StartIdx + NumVal];
679 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &
[all...] |
| RegBankSelect.cpp | 138 const iterator_range<SmallVectorImpl<unsigned>::const_iterator> &NewVRegs) {
143 assert(NewVRegs.begin() != NewVRegs.end() && "We should not have to repair");
148 unsigned Dst = *NewVRegs.begin();
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| RegAllocGreedy.cpp | 497 SmallVectorImpl<unsigned> &NewVRegs);
502 SmallVectorImpl<unsigned> &NewVRegs);
761 SmallVectorImpl<unsigned> &NewVRegs) {
780 evictInterference(VirtReg, Hint, NewVRegs);
797 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
[all...] |
| RegAllocPBQP.cpp | 641 SmallVector<unsigned, 8> NewVRegs;
642 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
643 Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
734 SmallVector<unsigned, 8> NewVRegs;
735 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
736 AnotherRoundNeeded |= !NewVRegs.empty();
[all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocGreedy.cpp | 380 SmallVectorImpl<unsigned> &NewVRegs);
385 SmallVectorImpl<unsigned> &NewVRegs);
620 SmallVectorImpl<unsigned> &NewVRegs) {
639 evictInterference(VirtReg, Hint, NewVRegs);
653 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
808 SmallVectorImpl<unsigned> &NewVRegs) {
840 NewVRegs.push_back(Intf->reg);
860 SmallVectorImpl<unsigned> &NewVRegs,
[all...] |
| RegAllocPBQP.cpp | 613 SmallVector<unsigned, 8> NewVRegs;
614 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
615 Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
693 SmallVector<unsigned, 8> NewVRegs;
694 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
695 AnotherRoundNeeded |= !NewVRegs.empty();
|
| InlineSpiller.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegBankSelect.h | 495 /// \p NewVRegs contains all the registers required to remap \p Reg.
496 /// In other words, the number of registers in NewVRegs must be equal
519 /// \pre NewVRegs.size() == ValMapping.BreakDown.size()
527 &NewVRegs);
|
| RegisterBankInfo.h | 194 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
198 SmallVector<unsigned, 8> NewVRegs;
210 /// Get the range in NewVRegs to store all the partial
220 /// spannig \p NumVal in NewVRegs.
221 /// \pre StartIdx + NumVal <= NewVRegs.size()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegBankSelect.h | 533 /// \p NewVRegs contains all the registers required to remap \p Reg.
534 /// In other words, the number of registers in NewVRegs must be equal
557 /// \pre NewVRegs.size() == ValMapping.BreakDown.size()
567 &NewVRegs);
|
| RegisterBankInfo.h | 278 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
284 SmallVector<unsigned, 8> NewVRegs;
299 /// Get the range in NewVRegs to store all the partial
309 /// spannig \p NumVal in NewVRegs.
310 /// \pre StartIdx + NumVal <= NewVRegs.size()
|
