| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| fd5_emit.c | 285 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
458 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
463 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
472 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
480 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
503 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
521 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
524 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
541 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
550 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2)
[all...] |
| fd5_compute.c | 69 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
72 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
77 OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
84 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
89 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
93 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
99 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
103 OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
106 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
113 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL_0, 2)
[all...] |
| fd5_gmem.c | 100 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(i), 5);
116 OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
125 OUT_PKT4(ring, REG_A5XX_RB_MRT_FLAG_BUFFER(i), 4);
153 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_BUFFER_INFO, 5);
164 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
167 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
173 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2);
180 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO, 3);
185 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO, 2)
[all...] |
| fd5_draw.c | 55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
205 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
208 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
211 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
214 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
217 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
220 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
223 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
231 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1)
[all...] |
| fd5_program.c | 372 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
389 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
392 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
404 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
421 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
424 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
428 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
432 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
436 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
440 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2)
[all...] |
| fd5_blitter.c | 161 OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
164 OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
169 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
172 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
175 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1);
178 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1);
181 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
184 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
187 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
190 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1)
[all...] |
| fd5_emit.h | 104 OUT_PKT4(ring, REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO, 5);
158 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
165 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
177 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
183 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
|
| fd5_query.c | 59 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_CONTROL, 1);
62 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
84 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_CONTROL, 1);
87 OUT_PKT4(ring, REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
|
| /external/mesa3d/src/gallium/drivers/freedreno/ |
| freedreno_util.h | 311 OUT_PKT4(struct fd_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
418 OUT_PKT4(ring, reg, 1);
|
