1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <stdio.h> 29 30 #include "pipe/p_video_codec.h" 31 32 #include "util/u_video.h" 33 #include "util/u_memory.h" 34 35 #include "vl/vl_video_buffer.h" 36 37 #include "r600_pipe_common.h" 38 #include "radeon_video.h" 39 #include "radeon_vcn_enc.h" 40 41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value)) 42 #define RADEON_ENC_BEGIN(cmd) { \ 43 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \ 44 RADEON_ENC_CS(cmd) 45 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 46 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 47 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \ 49 enc->total_task_size += *begin;} 50 51 static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 }; 52 static const unsigned index_to_shifts[4] = {24, 16, 8, 0}; 53 54 static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf, 55 enum radeon_bo_usage usage, enum radeon_bo_domain domain, 56 signed offset) 57 { 58 enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, 59 domain, RADEON_PRIO_VCE); 60 uint64_t addr; 61 addr = enc->ws->buffer_get_virtual_address(buf); 62 addr = addr + offset; 63 RADEON_ENC_CS(addr >> 32); 64 RADEON_ENC_CS(addr); 65 } 66 67 static void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set) 68 { 69 if (set != enc->emulation_prevention) { 70 enc->emulation_prevention = set; 71 enc->num_zeros = 0; 72 } 73 } 74 75 static void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte) 76 { 77 if (enc->byte_index == 0) 78 enc->cs->current.buf[enc->cs->current.cdw] = 0; 79 enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]); 80 enc->byte_index++; 81 82 if (enc->byte_index >= 4) { 83 enc->byte_index = 0; 84 enc->cs->current.cdw++; 85 } 86 } 87 88 static void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte) 89 { 90 if(enc->emulation_prevention) { 91 if((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) { 92 radeon_enc_output_one_byte(enc, 0x03); 93 enc->bits_output += 8; 94 enc->num_zeros = 0; 95 } 96 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0); 97 } 98 } 99 100 static void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, unsigned int num_bits) 101 { 102 unsigned int bits_to_pack = 0; 103 104 while(num_bits > 0) { 105 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits)); 106 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits; 107 108 if (bits_to_pack < num_bits) 109 value_to_pack = value_to_pack >> (num_bits - bits_to_pack); 110 111 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack); 112 num_bits -= bits_to_pack; 113 enc->bits_in_shifter += bits_to_pack; 114 115 while(enc->bits_in_shifter >= 8) { 116 unsigned char output_byte = (unsigned char)(enc->shifter >> 24); 117 enc->shifter <<= 8; 118 radeon_enc_emulation_prevention(enc, output_byte); 119 radeon_enc_output_one_byte(enc, output_byte); 120 enc->bits_in_shifter -= 8; 121 enc->bits_output += 8; 122 } 123 } 124 } 125 126 static void radeon_enc_reset(struct radeon_encoder *enc) 127 { 128 enc->emulation_prevention = false; 129 enc->shifter = 0; 130 enc->bits_in_shifter = 0; 131 enc->bits_output = 0; 132 enc->num_zeros = 0; 133 enc->byte_index = 0; 134 } 135 136 static void radeon_enc_byte_align(struct radeon_encoder *enc) 137 { 138 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8; 139 140 if (num_padding_zeros > 0) 141 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros); 142 } 143 144 static void radeon_enc_flush_headers(struct radeon_encoder *enc) 145 { 146 if (enc->bits_in_shifter != 0) { 147 unsigned char output_byte = (unsigned char)(enc->shifter >> 24); 148 radeon_enc_emulation_prevention(enc, output_byte); 149 radeon_enc_output_one_byte(enc, output_byte); 150 enc->bits_output += enc->bits_in_shifter; 151 enc->shifter = 0; 152 enc->bits_in_shifter = 0; 153 enc->num_zeros = 0; 154 } 155 156 if (enc->byte_index > 0) { 157 enc->cs->current.cdw++; 158 enc->byte_index = 0; 159 } 160 } 161 162 static void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value) 163 { 164 int x = -1; 165 unsigned int ue_code = value + 1; 166 value += 1; 167 168 while (value) { 169 value = (value >> 1); 170 x += 1; 171 } 172 173 unsigned int ue_length = (x << 1) + 1; 174 radeon_enc_code_fixed_bits(enc, ue_code, ue_length); 175 } 176 177 static void radeon_enc_code_se(struct radeon_encoder *enc, int value) 178 { 179 unsigned int v = 0; 180 181 if (value != 0) 182 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1)); 183 184 radeon_enc_code_ue(enc, v); 185 } 186 187 static void radeon_enc_session_info(struct radeon_encoder *enc) 188 { 189 unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) | 190 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT)); 191 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO); 192 RADEON_ENC_CS(interface_version); 193 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0); 194 RADEON_ENC_END(); 195 } 196 197 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback) 198 { 199 enc->enc_pic.task_info.task_id++; 200 201 if (need_feedback) 202 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1; 203 else 204 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0; 205 206 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO); 207 enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++]; 208 RADEON_ENC_CS(enc->enc_pic.task_info.task_id); 209 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks); 210 RADEON_ENC_END(); 211 } 212 213 static void radeon_enc_session_init(struct radeon_encoder *enc) 214 { 215 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; 216 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); 217 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); 218 enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width; 219 enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height; 220 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; 221 enc->enc_pic.session_init.pre_encode_chroma_enabled = false; 222 223 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT); 224 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); 225 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); 226 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); 227 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); 228 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); 229 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); 230 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); 231 RADEON_ENC_END(); 232 } 233 234 static void radeon_enc_layer_control(struct radeon_encoder *enc) 235 { 236 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1; 237 enc->enc_pic.layer_ctrl.num_temporal_layers = 1; 238 239 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL); 240 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); 241 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers); 242 RADEON_ENC_END(); 243 } 244 245 static void radeon_enc_layer_select(struct radeon_encoder *enc) 246 { 247 enc->enc_pic.layer_sel.temporal_layer_index = 0; 248 249 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT); 250 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index); 251 RADEON_ENC_END(); 252 } 253 254 static void radeon_enc_slice_control(struct radeon_encoder *enc) 255 { 256 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS; 257 enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16; 258 259 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL); 260 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode); 261 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice); 262 RADEON_ENC_END(); 263 } 264 265 static void radeon_enc_spec_misc(struct radeon_encoder *enc) 266 { 267 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0; 268 enc->enc_pic.spec_misc.cabac_enable = 0; 269 enc->enc_pic.spec_misc.cabac_init_idc = 0; 270 enc->enc_pic.spec_misc.half_pel_enabled = 1; 271 enc->enc_pic.spec_misc.quarter_pel_enabled = 1; 272 enc->enc_pic.spec_misc.profile_idc = profiles[enc->base.profile - PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]; 273 enc->enc_pic.spec_misc.level_idc = enc->base.level; 274 275 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC); 276 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag); 277 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable); 278 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc); 279 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled); 280 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled); 281 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc); 282 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc); 283 RADEON_ENC_END(); 284 } 285 286 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic) 287 { 288 switch(pic->rate_ctrl.rate_ctrl_method) { 289 case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE: 290 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE; 291 break; 292 case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP: 293 case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT: 294 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR; 295 break; 296 case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP: 297 case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE: 298 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR; 299 break; 300 default: 301 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE; 302 } 303 304 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv; 305 306 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT); 307 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method); 308 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level); 309 RADEON_ENC_END(); 310 } 311 312 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic) 313 { 314 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate; 315 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate; 316 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num; 317 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den; 318 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size; 319 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture; 320 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer; 321 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction; 322 323 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT); 324 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate); 325 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate); 326 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num); 327 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den); 328 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size); 329 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture); 330 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer); 331 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional); 332 RADEON_ENC_END(); 333 } 334 335 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc) 336 { 337 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0; 338 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0; 339 enc->enc_pic.h264_deblock.beta_offset_div2 = 0; 340 enc->enc_pic.h264_deblock.cb_qp_offset = 0; 341 enc->enc_pic.h264_deblock.cr_qp_offset = 0; 342 343 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER); 344 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc); 345 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2); 346 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2); 347 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset); 348 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset); 349 RADEON_ENC_END(); 350 } 351 352 static void radeon_enc_quality_params(struct radeon_encoder *enc) 353 { 354 enc->enc_pic.quality_params.vbaq_mode = 0; 355 enc->enc_pic.quality_params.scene_change_sensitivity = 0; 356 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0; 357 358 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS); 359 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode); 360 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity); 361 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval); 362 RADEON_ENC_END(); 363 } 364 365 static void radeon_enc_nalu_sps(struct radeon_encoder *enc) 366 { 367 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU); 368 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS); 369 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; 370 radeon_enc_reset(enc); 371 radeon_enc_set_emulation_prevention(enc, false); 372 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); 373 radeon_enc_code_fixed_bits(enc, 0x67, 8); 374 radeon_enc_byte_align(enc); 375 radeon_enc_set_emulation_prevention(enc, true); 376 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8); 377 radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline 378 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8); 379 radeon_enc_code_ue(enc, 0x0); 380 381 if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 || 382 enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 || 383 enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 || 384 enc->enc_pic.spec_misc.profile_idc == 138) { 385 radeon_enc_code_ue(enc, 0x1); 386 radeon_enc_code_ue(enc, 0x0); 387 radeon_enc_code_ue(enc, 0x0); 388 radeon_enc_code_fixed_bits(enc, 0x0, 2); 389 } 390 391 radeon_enc_code_ue(enc, 1); 392 radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type); 393 394 if (enc->enc_pic.pic_order_cnt_type == 0) 395 radeon_enc_code_ue(enc, 1); 396 397 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); 398 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1); 399 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1)); 400 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1)); 401 bool progressive_only = true; 402 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1); 403 404 if (!progressive_only) 405 radeon_enc_code_fixed_bits(enc, 0x0, 1); 406 407 radeon_enc_code_fixed_bits(enc, 0x1, 1); 408 409 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || 410 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { 411 radeon_enc_code_fixed_bits(enc, 0x1, 1); 412 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); 413 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); 414 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); 415 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); 416 } else 417 radeon_enc_code_fixed_bits(enc, 0x0, 1); 418 419 radeon_enc_code_fixed_bits(enc, 0x1, 1); 420 radeon_enc_code_fixed_bits(enc, 0x0, 1); 421 radeon_enc_code_fixed_bits(enc, 0x0, 1); 422 radeon_enc_code_fixed_bits(enc, 0x0, 1); 423 radeon_enc_code_fixed_bits(enc, 0x0, 1); 424 radeon_enc_code_fixed_bits(enc, 0x0, 1); 425 radeon_enc_code_fixed_bits(enc, 0x0, 1); 426 radeon_enc_code_fixed_bits(enc, 0x0, 1); 427 radeon_enc_code_fixed_bits(enc, 0x0, 1); 428 radeon_enc_code_fixed_bits(enc, 0x1, 1); 429 radeon_enc_code_fixed_bits(enc, 0x1, 1); 430 radeon_enc_code_ue(enc, 0x0); 431 radeon_enc_code_ue(enc, 0x0); 432 radeon_enc_code_ue(enc, 16); 433 radeon_enc_code_ue(enc, 16); 434 radeon_enc_code_ue(enc, 0x0); 435 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); 436 437 radeon_enc_code_fixed_bits(enc, 0x1, 1); 438 439 radeon_enc_byte_align(enc); 440 radeon_enc_flush_headers(enc); 441 *size_in_bytes = (enc->bits_output + 7) / 8; 442 RADEON_ENC_END(); 443 } 444 445 static void radeon_enc_nalu_pps(struct radeon_encoder *enc) 446 { 447 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU); 448 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS); 449 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; 450 radeon_enc_reset(enc); 451 radeon_enc_set_emulation_prevention(enc, false); 452 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); 453 radeon_enc_code_fixed_bits(enc, 0x68, 8); 454 radeon_enc_byte_align(enc); 455 radeon_enc_set_emulation_prevention(enc, true); 456 radeon_enc_code_ue(enc, 0x0); 457 radeon_enc_code_ue(enc, 0x0); 458 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1); 459 radeon_enc_code_fixed_bits(enc, 0x0, 1); 460 radeon_enc_code_ue(enc, 0x0); 461 radeon_enc_code_ue(enc, 0x0); 462 radeon_enc_code_ue(enc, 0x0); 463 radeon_enc_code_fixed_bits(enc, 0x0, 1); 464 radeon_enc_code_fixed_bits(enc, 0x0, 2); 465 radeon_enc_code_se(enc, 0x0); 466 radeon_enc_code_se(enc, 0x0); 467 radeon_enc_code_se(enc, 0x0); 468 radeon_enc_code_fixed_bits(enc, 0x1, 1); 469 radeon_enc_code_fixed_bits(enc, 0x0, 1); 470 radeon_enc_code_fixed_bits(enc, 0x0, 1); 471 472 radeon_enc_code_fixed_bits(enc, 0x1, 1); 473 474 radeon_enc_byte_align(enc); 475 radeon_enc_flush_headers(enc); 476 *size_in_bytes = (enc->bits_output + 7) / 8; 477 RADEON_ENC_END(); 478 } 479 480 static void radeon_enc_slice_header(struct radeon_encoder *enc) 481 { 482 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0}; 483 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0}; 484 unsigned int inst_index = 0; 485 unsigned int bit_index = 0; 486 unsigned int bits_copied = 0; 487 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER); 488 radeon_enc_reset(enc); 489 radeon_enc_set_emulation_prevention(enc, false); 490 491 if (enc->enc_pic.is_idr) 492 radeon_enc_code_fixed_bits(enc, 0x65, 8); 493 else if (enc->enc_pic.not_referenced) 494 radeon_enc_code_fixed_bits(enc, 0x01, 8); 495 else 496 radeon_enc_code_fixed_bits(enc, 0x41, 8); 497 498 radeon_enc_flush_headers(enc); 499 bit_index ++; 500 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY; 501 num_bits[inst_index] = enc->bits_output - bits_copied; 502 bits_copied = enc->bits_output; 503 inst_index++; 504 505 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB; 506 inst_index++; 507 508 switch(enc->enc_pic.picture_type) { 509 case PIPE_H264_ENC_PICTURE_TYPE_I: 510 case PIPE_H264_ENC_PICTURE_TYPE_IDR: 511 radeon_enc_code_fixed_bits(enc, 0x08, 7); 512 break; 513 case PIPE_H264_ENC_PICTURE_TYPE_P: 514 case PIPE_H264_ENC_PICTURE_TYPE_SKIP: 515 radeon_enc_code_fixed_bits(enc, 0x06, 5); 516 break; 517 case PIPE_H264_ENC_PICTURE_TYPE_B: 518 radeon_enc_code_fixed_bits(enc, 0x07, 5); 519 break; 520 default: 521 radeon_enc_code_fixed_bits(enc, 0x08, 7); 522 } 523 524 radeon_enc_code_ue(enc, 0x0); 525 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5); 526 527 if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) { 528 radeon_enc_code_fixed_bits(enc, 0x1, 1); 529 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1); 530 } 531 532 if (enc->enc_pic.is_idr) 533 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame); 534 535 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame; 536 537 if (enc->enc_pic.pic_order_cnt_type == 0) 538 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5); 539 540 if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) { 541 radeon_enc_code_fixed_bits(enc, 0x0, 1); 542 543 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) { 544 radeon_enc_code_fixed_bits(enc, 0x1, 1); 545 radeon_enc_code_ue(enc, 0x0); 546 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1)); 547 radeon_enc_code_ue(enc, 0x3); 548 } else 549 radeon_enc_code_fixed_bits(enc, 0x0, 1); 550 } 551 552 if (enc->enc_pic.is_idr) { 553 radeon_enc_code_fixed_bits(enc, 0x0, 1); 554 radeon_enc_code_fixed_bits(enc, 0x0, 1); 555 } else 556 radeon_enc_code_fixed_bits(enc, 0x0, 1); 557 558 if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable)) 559 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc); 560 561 radeon_enc_flush_headers(enc); 562 bit_index ++; 563 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY; 564 num_bits[inst_index] = enc->bits_output - bits_copied; 565 bits_copied = enc->bits_output; 566 inst_index++; 567 568 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA; 569 inst_index++; 570 571 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0); 572 573 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) { 574 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2); 575 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2); 576 } 577 578 radeon_enc_flush_headers(enc); 579 bit_index ++; 580 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY; 581 num_bits[inst_index] = enc->bits_output - bits_copied; 582 bits_copied = enc->bits_output; 583 inst_index++; 584 585 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END; 586 587 for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++) 588 RADEON_ENC_CS(0x00000000); 589 590 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) { 591 RADEON_ENC_CS(instruction[j]); 592 RADEON_ENC_CS(num_bits[j]); 593 } 594 595 RADEON_ENC_END(); 596 } 597 598 static void radeon_enc_ctx(struct radeon_encoder *enc) 599 { 600 enc->enc_pic.ctx_buf.swizzle_mode = 0; 601 enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment); 602 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment); 603 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2; 604 605 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER); 606 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); 607 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); 608 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); 609 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch); 610 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures); 611 /* reconstructed_picture_1_luma_offset */ 612 RADEON_ENC_CS(0x00000000); 613 /* reconstructed_picture_1_chroma_offset */ 614 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16)); 615 /* reconstructed_picture_2_luma_offset */ 616 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2); 617 /* reconstructed_picture_2_chroma_offset */ 618 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2); 619 620 for (int i = 0; i < 136 ; i++) 621 RADEON_ENC_CS(0x00000000); 622 623 RADEON_ENC_END(); 624 } 625 626 static void radeon_enc_bitstream(struct radeon_encoder *enc) 627 { 628 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR; 629 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size; 630 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0; 631 632 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER); 633 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode); 634 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0); 635 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size); 636 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset); 637 RADEON_ENC_END(); 638 } 639 640 static void radeon_enc_feedback(struct radeon_encoder *enc) 641 { 642 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR; 643 enc->enc_pic.fb_buf.feedback_buffer_size = 16; 644 enc->enc_pic.fb_buf.feedback_data_size = 40; 645 646 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER); 647 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode); 648 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0); 649 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size); 650 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size); 651 RADEON_ENC_END(); 652 } 653 654 static void radeon_enc_intra_refresh(struct radeon_encoder *enc) 655 { 656 enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE; 657 enc->enc_pic.intra_ref.offset = 0; 658 enc->enc_pic.intra_ref.region_size = 0; 659 660 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH); 661 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode); 662 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset); 663 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size); 664 RADEON_ENC_END(); 665 } 666 667 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic) 668 { 669 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames; 670 enc->enc_pic.rc_per_pic.min_qp_app = 0; 671 enc->enc_pic.rc_per_pic.max_qp_app = 51; 672 enc->enc_pic.rc_per_pic.max_au_size = 0; 673 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable; 674 enc->enc_pic.rc_per_pic.skip_frame_enable = false; 675 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd; 676 677 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE); 678 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp); 679 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app); 680 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app); 681 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size); 682 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data); 683 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable); 684 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd); 685 RADEON_ENC_END(); 686 } 687 688 static void radeon_enc_encode_params(struct radeon_encoder *enc) 689 { 690 switch(enc->enc_pic.picture_type) { 691 case PIPE_H264_ENC_PICTURE_TYPE_I: 692 case PIPE_H264_ENC_PICTURE_TYPE_IDR: 693 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; 694 break; 695 case PIPE_H264_ENC_PICTURE_TYPE_P: 696 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P; 697 break; 698 case PIPE_H264_ENC_PICTURE_TYPE_SKIP: 699 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP; 700 break; 701 case PIPE_H264_ENC_PICTURE_TYPE_B: 702 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B; 703 break; 704 default: 705 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; 706 } 707 708 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; 709 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; 710 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; 711 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR; 712 713 if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) 714 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF; 715 else 716 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2; 717 718 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2; 719 720 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS); 721 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); 722 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); 723 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); 724 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); 725 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch); 726 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch); 727 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode); 728 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index); 729 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index); 730 RADEON_ENC_END(); 731 } 732 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc) 733 { 734 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; 735 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE; 736 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; 737 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF; 738 739 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS); 740 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure); 741 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode); 742 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure); 743 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index); 744 RADEON_ENC_END(); 745 } 746 747 static void radeon_enc_op_init(struct radeon_encoder *enc) 748 { 749 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE); 750 RADEON_ENC_END(); 751 } 752 753 static void radeon_enc_op_close(struct radeon_encoder *enc) 754 { 755 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION); 756 RADEON_ENC_END(); 757 } 758 759 static void radeon_enc_op_enc(struct radeon_encoder *enc) 760 { 761 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE); 762 RADEON_ENC_END(); 763 } 764 765 static void radeon_enc_op_init_rc(struct radeon_encoder *enc) 766 { 767 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC); 768 RADEON_ENC_END(); 769 } 770 771 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc) 772 { 773 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL); 774 RADEON_ENC_END(); 775 } 776 777 static void radeon_enc_op_speed(struct radeon_encoder *enc) 778 { 779 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE); 780 RADEON_ENC_END(); 781 } 782 783 static void begin(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic) 784 { 785 radeon_enc_session_info(enc); 786 enc->total_task_size = 0; 787 radeon_enc_task_info(enc, enc->need_feedback); 788 radeon_enc_op_init(enc); 789 radeon_enc_session_init(enc); 790 radeon_enc_layer_control(enc); 791 radeon_enc_slice_control(enc); 792 radeon_enc_spec_misc(enc); 793 radeon_enc_rc_session_init(enc, pic); 794 radeon_enc_deblocking_filter_h264(enc); 795 radeon_enc_quality_params(enc); 796 radeon_enc_layer_select(enc); 797 radeon_enc_rc_layer_init(enc, pic); 798 radeon_enc_layer_select(enc); 799 radeon_enc_rc_per_pic(enc, pic); 800 radeon_enc_op_init_rc(enc); 801 radeon_enc_op_init_rc_vbv(enc); 802 *enc->p_task_size = (enc->total_task_size); 803 } 804 805 static void encode(struct radeon_encoder *enc) 806 { 807 radeon_enc_session_info(enc); 808 enc->total_task_size = 0; 809 radeon_enc_task_info(enc, enc->need_feedback); 810 811 if (enc->enc_pic.is_idr) { 812 radeon_enc_nalu_sps(enc); 813 radeon_enc_nalu_pps(enc); 814 } 815 816 radeon_enc_slice_header(enc); 817 radeon_enc_ctx(enc); 818 radeon_enc_bitstream(enc); 819 radeon_enc_feedback(enc); 820 radeon_enc_intra_refresh(enc); 821 radeon_enc_encode_params(enc); 822 radeon_enc_encode_params_h264(enc); 823 radeon_enc_op_speed(enc); 824 radeon_enc_op_enc(enc); 825 *enc->p_task_size = (enc->total_task_size); 826 } 827 828 static void destroy(struct radeon_encoder *enc) 829 { 830 radeon_enc_session_info(enc); 831 enc->total_task_size = 0; 832 radeon_enc_task_info(enc, enc->need_feedback); 833 radeon_enc_op_close(enc); 834 *enc->p_task_size = (enc->total_task_size); 835 } 836 837 void radeon_enc_1_2_init(struct radeon_encoder *enc) 838 { 839 enc->begin = begin; 840 enc->encode = encode; 841 enc->destroy = destroy; 842 } 843
