| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 196 // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
198 SDIVREM, UDIVREM,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 202 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
204 SDIVREM, UDIVREM,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 208 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
210 SDIVREM, UDIVREM,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 81 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
82 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 155 setOperationAction(ISD::SDIVREM, VT, Custom);
333 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
335 bool IsSigned = (Opcode == ISD::SDIVREM);
697 case ISD::SDIVREM:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 93 SDIVREM,
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 184 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
190 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
196 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
202 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
208 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 150 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
156 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 157 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
163 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 186 case ISD::SDIVREM: return "sdivrem";
|
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeVectorOps.cpp | 269 case ISD::SDIVREM:
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 603 case ISD::SDIVREM: {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 219 case ISD::SDIVREM: return "sdivrem";
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 87 setOperationAction(ISD::SDIVREM, VT, Expand);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 198 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
205 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
233 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
280 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
456 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 131 setOperationAction(ISD::SDIVREM, MVT::i8, Promote);
137 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 300 setOperationAction(ISD::SDIVREM, VT, Custom);
385 setOperationAction(ISD::SDIVREM, VT, Custom);
711 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 103 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 110 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 219 setTargetDAGCombine(ISD::SDIVREM);
424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
648 case ISD::SDIVREM:
[all...] |
