| /external/e2fsprogs/lib/ext2fs/ |
| icount.c | 35 * one, and then use a sorted list to store the counts for inodes
719 #define STORE 0x02
731 { STORE, 42, 42, 42 },
732 { STORE, 1, 1, 1 },
733 { STORE, 2, 2, 2 },
734 { STORE, 3, 3, 3 },
735 { STORE, 10, 1, 1 },
736 { STORE, 42, 0, 0 },
757 { STORE, 1, 1, 1 },
758 { STORE, 2, 2, 2 }
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| hsw_queryobj.c | 46 MI_MATH_ALU2(STORE, R1, ACCU),
50 MI_MATH_ALU2(STORE, R1, ACCU),
54 MI_MATH_ALU2(STORE, R1, ACCU),
59 MI_MATH_ALU2(STORE, R1, ACCU),
63 MI_MATH_ALU2(STORE, R2, ACCU),
68 MI_MATH_ALU2(STORE, R2, ACCU),
73 MI_MATH_ALU2(STORE, R0, ACCU),
95 MI_MATH_ALU2(STORE, R0, ACCU),
123 MI_MATH_ALU2(STORE, R0, ACCU),
175 MI_MATH_ALU2(STORE, R0, ACCU)
[all...] |
| hsw_sol.c | 39 * We store several values in obj->prim_count_bo:
54 * Store the SO_NUM_PRIMS_WRITTEN counters for each stream (4 uint64_t values)
78 * (by multiplying by the number of vertices per primitive), and store
109 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU));
114 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
131 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
140 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU));
144 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
147 /* Store it to the final result */
185 /* Store the new starting value of the SO_NUM_PRIMS_WRITTEN counters. *
[all...] |
| /external/llvm/test/MC/Mips/ |
| cprestore-noreorder-noat.s | 12 # RUN: FileCheck %s -check-prefix=NO-STORE
15 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=NO-STORE
29 # NO-STORE-NOT: sw $gp, 8($sp)
48 # NO-STORE-NOT: sw $gp,
|
| cprestore-noreorder.s | 5 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
34 # CHECK-FOR-STORE: sw $gp, 8($sp)
|
| cprestore-reorder.s | 5 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
35 # CHECK-FOR-STORE: sw $gp, 8($sp)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| cprestore-noreorder-noat.s | 12 # RUN: FileCheck %s -check-prefix=NO-STORE
15 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=NO-STORE
29 # NO-STORE-NOT: sw $gp, 8($sp)
48 # NO-STORE-NOT: sw $gp,
|
| cprestore-noreorder.s | 5 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
34 # CHECK-FOR-STORE: sw $gp, 8($sp)
|
| cprestore-reorder.s | 5 # RUN: llvm-objdump -d -r - | FileCheck %s -check-prefix=CHECK-FOR-STORE
35 # CHECK-FOR-STORE: sw $gp, 8($sp)
|
| /external/elfutils/libelf/ |
| gelf_xlate.c | 68 #define STORE(Bits, ptr, val) (*(uint##Bits##_t *) ptr = val)
80 #define STORE(Bits, ptr, val) (((union unaligned *) ptr)->u##Bits = val)
99 case 2: STORE (16, dest, bswap_16 (FETCH (16, ptr))); break; \
100 case 4: STORE (32, dest, bswap_32 (FETCH (32, ptr))); break; \
101 case 8: STORE (64, dest, bswap_64 (FETCH (64, ptr))); break; \
|
| /external/libxaac/decoder/armv7/ |
| ixheaacd_harm_idx_zerotwolp.s | 62 B STORE
74 STORE:
|
| /external/elfutils/libcpu/ |
| bpf_disasm.c | 69 #define STORE(T, S) "*(" #T " *)(" REG(1) OFF(3) ") = " S
410 code_fmt = STORE(u8, REG(2));
413 code_fmt = STORE(u16, REG(2));
416 code_fmt = STORE(u32, REG(2));
419 code_fmt = STORE(u64, REG(2));
430 code_fmt = STORE(u8, IMMS(2));
433 code_fmt = STORE(u16, IMMS(2));
436 code_fmt = STORE(u32, IMMS(2));
439 code_fmt = STORE(u64, IMMS(2));
|
| /external/mesa3d/src/compiler/nir/ |
| nir_intrinsics.h | 182 * Image load, store and atomic intrinsics.
191 * in use are undefined. Image store takes an additional four-component
422 * load/store intrinsics. Typically, this is vec4 units for things such as
457 * to store and the second (and possibly third) source specify where to store
462 #define STORE(name, srcs, num_indices, idx0, idx1, idx2, flags) \
466 STORE(output, 2, 3, BASE, WRMASK, COMPONENT, 0)
470 STORE(per_vertex_output, 3, 3, BASE, WRMASK, COMPONENT, 0)
472 STORE(ssbo, 3, 1, WRMASK, xx, xx, 0)
474 STORE(shared, 2, 2, BASE, WRMASK, xx, 0
[all...] |
| /external/webp/src/dsp/ |
| dec.c | 29 #define STORE(x, y, v) \
34 STORE(0, y, DC + (d)); \
35 STORE(1, y, DC + (c)); \
36 STORE(2, y, DC - (c)); \
37 STORE(3, y, DC - (d)); \
74 STORE(0, 0, a + d);
75 STORE(1, 0, b + c);
76 STORE(2, 0, b - c);
77 STORE(3, 0, a - d);
118 STORE(i, j, DC)
[all...] |
| /external/v8/src/compiler/ |
| machine-operator.cc | 524 #define STORE(Type) \
525 struct Store##Type##Operator : public Operator1<StoreRepresentation> { \
526 explicit Store##Type##Operator(WriteBarrierKind write_barrier_kind) \
530 "Store", 3, 1, 1, 0, 1, 0, \
534 struct Store##Type##NoWriteBarrier##Operator final \
535 : public Store##Type##Operator { \
536 Store##Type##NoWriteBarrier##Operator() \
537 : Store##Type##Operator(kNoWriteBarrier) {} \
539 struct Store##Type##MapWriteBarrier##Operator final \
540 : public Store##Type##Operator {
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
| streamout_jit.cpp | 153 // store to output buffer
197 STORE(numPrimStorageNeeded, pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimStorageNeeded });
216 STORE(numPrimsWritten, pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimsWritten });
257 STORE(streamOffset, pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset });
|
| /external/u-boot/arch/riscv/include/asm/ |
| encoding.h | 123 #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
126 ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| SlotIndexes.h | 86 enum Slot { LOAD, USE, DEF, STORE, NUM };
209 /// isStore - Return true if this is a STORE slot.
211 return getSlot() == STORE;
246 /// Returns the index of the STORE slot for the instruction pointed to by
249 return SlotIndex(&entry(), SlotIndex::STORE);
254 /// index is a STORE, the first slot for the next instruction.
260 if (s == SlotIndex::STORE) {
281 return SlotIndex(entry().getPrev(), SlotIndex::STORE);
|
| ISDOpcodes.h | 454 // LOAD and STORE have token chains as their first operand, then the same
455 // operands as an LLVM load/store instruction, then an offset node that
458 LOAD, STORE,
592 // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
593 // store-store, device)
610 // This corresponds to "store atomic" instruction.
644 /// MemIndexedMode enum - This enum defines the load / store indexed
647 /// UNINDEXED "Normal" load / store. The effective address is alread
[all...] |
| /external/pdfium/third_party/libopenjpeg20/ |
| dwt.c | 608 #define STORE(x,y) _mm256_store_si256((VREG*)(x),(y))
618 #define STORE(x,y) _mm_store_si128((VREG*)(x),(y))
674 /* fashion. But stores in tmp can be done with aligned store, since */
703 STORE(tmp + PARALLEL_COLS_53 * (i + 0), s0c_0);
704 STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0c_1);
707 STORE(tmp + PARALLEL_COLS_53 * (i + 1) + 0,
709 STORE(tmp + PARALLEL_COLS_53 * (i + 1) + VREG_INT_COUNT,
713 STORE(tmp + PARALLEL_COLS_53 * (i + 0) + 0, s0n_0);
714 STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0n_1);
721 STORE(tmp + PARALLEL_COLS_53 * (len - 1), tmp_len_minus_1)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIMemoryLegalizer.cpp | 59 STORE = 1u << 1,
60 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ STORE)
237 /// \returns Store info if \p MI is a store operation, "None" otherwise.
381 /// Expands store operation \p MI. Returns true if instructions are
879 SIMemOp::LOAD | SIMemOp::STORE,
918 SIMemOp::LOAD | SIMemOp::STORE,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 68 /// Used on Mips Load/Store instructions
224 case ISD::STORE:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGAddressAnalysis.cpp | 121 case ISD::STORE: {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 76 /// Used on Mips Load/Store instructions
247 case ISD::STORE:
|
| /external/tensorflow/tensorflow/core/kernels/ |
| sparse_matmul_op.cc | 98 // For each block, we store all the non zero entries in data/data3 vector and
105 // vectors respectively. To identify block boundaries, we store the block
282 #define STORE(x, y) Eigen::internal::pstore<float>(x, y);
420 STORE(*out, c1);
421 STORE(*out + kNumOperands, c2);
452 STORE(*out, c1);
453 STORE(*out + kNumOperands, c2);
502 STORE(*out, c1);
503 STORE(*out + kNumOperands, c2);
504 STORE(*out + 2 * kNumOperands, c3)
[all...] |
