| /external/swiftshader/third_party/subzero/src/ |
| IcePhiLoweringImpl.h | 65 auto *SrcVec = llvm::cast<VariableVecOn32>(Src);
66 PhiElem->addArgument(SrcVec->getContainers()[Idx], Label);
|
| IceTargetLoweringMIPS32.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600OptimizeVectorRegisters.cpp | 187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
199 .addReg(SrcVec)
212 SrcVec = DstReg;
215 BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec);
|
| SILowerControlFlow.cpp | 633 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
637 std::tie(Reg, Offset) = computeIndirectRegAndOffset(SrcVec->getReg(), Offset);
643 .addReg(Reg, getUndefRegState(SrcVec->isUndef()));
650 .addReg(Reg, getUndefRegState(SrcVec->isUndef()))
651 .addReg(SrcVec->getReg(), RegState::Implicit);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600OptimizeVectorRegisters.cpp | 211 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
223 .addReg(SrcVec)
234 SrcVec = DstReg;
237 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
|
| SIISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Verifier.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Verifier.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| Verifier.cpp | [all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
