| /external/syzkaller/pkg/ifuzz/ |
| decode.go | 33 vex := false
35 // There are only 2 32-bit instructions that look like VEX-prefixed but are actually not: LDS, LES.
36 // They always reference memory (mod!=3), but all VEX instructions have "mod=3" where LDS/LES would have mod.
38 vex = true
43 vex = true
47 if vex {
54 return 0, fmt.Errorf("bad VEX/XOP prefix")
99 if vex != (insn.Vex != 0) {
102 if vex && insn.VexMap != vexMap
[all...] |
| encode.go | 41 if insn.Vex == 0 {
116 // VEX/VOP
117 code = append(code, insn.Vex)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 377 /// VEX - The opcode prefix used by AVX instructions
379 VEX = 1U << 0,
395 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
401 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
|
| X86MCCodeEmitter.cpp | 55 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
59 // VEX.VVVV => XMM9 => ~9
385 /// called VEX.
420 // VEX_5M (VEX m-mmmmm field):
430 // VEX_4V (VEX vvvv field): a register specifier
479 case X86II::A6: // Bypass: Not used by VEX
480 case X86II::A7: // Bypass: Not used by VEX
481 case X86II::TB: // Bypass: Not used by VEX
595 // VEX opcode prefix can have 2 or 3 bytes
608 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefi
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86InstrFMA3Info.cpp | 137 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX ||
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 133 VEX = 1, XOP = 2, EVEX = 3
182 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
|
| X86FoldTablesEmitter.cpp | 307 // Function object - Operator() returns true if the given VEX instruction
325 // VEX/EVEX fields
486 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX &&
488 // Instructions with VEX encoding do not require alignment.
|
| X86RecognizableInstr.cpp | 128 // Special case since there is no attribute class for 64-bit and VEX
163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
256 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
503 // - In AVX, there is a register operand in the VEX.vvvv field here -
515 // in ModRMVEX and the one above the one in the VEX.VVVV field
524 // - In AVX, there is a register operand in the VEX.vvvv field here -
537 // in ModRMVEX and the one above the one in the VEX.VVVV field
546 // - In AVX, there is a register operand in the VEX.vvvv field here -
561 // in ModRMVEX and the one above the one in the VEX.VVVV fiel
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 387 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
465 // VEX - encoding using 0xC4/0xC5
466 VEX = 1 << EncodingShift,
492 /// operand 3 with VEX.vvvv.
502 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
509 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
519 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
|
| X86MCCodeEmitter.cpp | 595 /// called VEX.
600 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
636 // VEX_5M (VEX m-mmmmm field):
657 // VEX_4V (VEX vvvv field): a register specifier
890 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
891 // VEX opcode prefix can have 2 or 3 bytes
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 299 /// operand 3 with VEX.VVVV and load from memory.
328 /// operand 3 with VEX.VVVV and do not load from memory.
431 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
518 // VEX - encoding using 0xC4/0xC5
519 VEX = 1 << EncodingShift,
544 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
|
| X86MCCodeEmitter.cpp | 629 /// called VEX.
634 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
668 // VEX_5M (VEX m-mmmmm field):
689 // VEX_4V (VEX vvvv field): a register specifier
[all...] |
| X86MCTargetDesc.cpp | 397 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
413 // Early exit if this instruction has no vex/evex/xop prefix.
417 // All VEX and EVEX encoded instructions are defined to zero the high bits
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.cpp | 127 VEX = 1, XOP = 2, EVEX = 3
255 // Special case since there is no attribute class for 64-bit and VEX
290 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
291 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
376 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
608 // - In AVX, there is a register operand in the VEX.vvvv field here -
620 // in ModRMVEX and the one above the one in the VEX.VVVV field
629 // - In AVX, there is a register operand in the VEX.vvvv field here -
642 // in ModRMVEX and the one above the one in the VEX.VVVV field
651 // - In AVX, there is a register operand in the VEX.vvvv field here
[all...] |
| /external/syzkaller/pkg/ifuzz/gen/ |
| gen.go | 303 // VOP/VEX
305 insn.Vex = 0x8f
308 insn.Vex = 0xc4
310 insn.Vex = 0xc4
|
| /external/capstone/bindings/vb6/ |
| mx86.bas | 392 ' This contains VEX opcode as well.
[all...] |
| /external/libaom/libaom/third_party/x86inc/ |
| x86inc.asm | [all...] |
| /external/libvpx/libvpx/third_party/x86inc/ |
| x86inc.asm | [all...] |
