| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 109 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
115 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
128 else if (LocVT == MVT::f128 && Offset < 16*8)
512 } else if (VA.getValVT() == MVT::f128) {
513 report_fatal_error("SPARCv8 does not handle f128 in calls; "
[all...] |
| SparcISelLowering.h | 196 // Do not shrink FP constpool if VT == MVT::f128.
198 return VT != MVT::f128;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 186 if (RetVT == MVT::f128)
191 if (RetVT == MVT::f128)
196 if (RetVT == MVT::f128)
213 if (OpVT == MVT::f128)
222 if (OpVT == MVT::f128)
229 if (OpVT == MVT::f128)
234 if (OpVT == MVT::f128)
265 } else if (OpVT == MVT::f128) {
307 } else if (OpVT == MVT::f128) {
335 if (RetVT == MVT::f128)
[all...] |
| ValueTypes.cpp | 134 case MVT::f128: return "f128";
218 case MVT::f128: return Type::getFP128Ty(Context);
295 case Type::FP128TyID: return MVT(MVT::f128);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 107 assert((LocVT == MVT::f32 || LocVT == MVT::f128
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
113 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
126 else if (LocVT == MVT::f128 && Offset < 16*8)
518 } else if (VA.getValVT() == MVT::f128) {
519 report_fatal_error("SPARCv8 does not handle f128 in calls; "
[all...] |
| SparcISelLowering.h | 196 // Do not shrink FP constpool if VT == MVT::f128.
198 return VT != MVT::f128;
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| ValueTypes.cpp | 114 case MVT::f128: return "f128";
164 case MVT::f128: return Type::getFP128Ty(Context);
209 case Type::FP128TyID: return MVT(MVT::f128);
|
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 508 if (RetVT == MVT::f128)
513 if (RetVT == MVT::f128)
532 if (OpVT == MVT::f128)
541 if (OpVT == MVT::f128)
548 if (OpVT == MVT::f128)
581 } else if (OpVT == MVT::f128) {
623 } else if (OpVT == MVT::f128) {
651 if (RetVT == MVT::f128)
662 if (RetVT == MVT::f128)
673 if (RetVT == MVT::f128)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 53 f128 = 11, // This is a 128 bit floating point value
479 case f128:
565 return MVT::f128;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 139 case MVT::f128: return "f128";
220 case MVT::f128: return Type::getFP128Ty(Context);
295 case Type::FP128TyID: return MVT(MVT::f128);
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ValueTypes.h | 51 f128 = 10, // This is a 128 bit floating point value enumerator in enum:llvm::MVT::SimpleValueType
269 case f128:
311 return MVT::f128;
404 /// with 128 bits - this returns f128 rather than ppcf128.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
|
| AArch64ISelLowering.cpp | 78 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
141 // Virtually no operation on f128 is legal, but LLVM can't expand them when
143 setOperationAction(ISD::FABS, MVT::f128, Expand);
144 setOperationAction(ISD::FADD, MVT::f128, Custom);
145 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
146 setOperationAction(ISD::FCOS, MVT::f128, Expand);
147 setOperationAction(ISD::FDIV, MVT::f128, Custom);
148 setOperationAction(ISD::FMA, MVT::f128, Expand);
149 setOperationAction(ISD::FMUL, MVT::f128, Custom);
150 setOperationAction(ISD::FNEG, MVT::f128, Expand)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
|
| AArch64ISelLowering.cpp | 137 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
208 // Virtually no operation on f128 is legal, but LLVM can't expand them when
210 setOperationAction(ISD::FABS, MVT::f128, Expand);
211 setOperationAction(ISD::FADD, MVT::f128, Custom);
212 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
213 setOperationAction(ISD::FCOS, MVT::f128, Expand);
214 setOperationAction(ISD::FDIV, MVT::f128, Custom);
215 setOperationAction(ISD::FMA, MVT::f128, Expand);
216 setOperationAction(ISD::FMUL, MVT::f128, Custom);
217 setOperationAction(ISD::FNEG, MVT::f128, Expand)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenCallingConv.inc | 74 LocVT = MVT::f128;
245 if (LocVT == MVT::f128 ||
292 if (LocVT == MVT::f128 ||
325 LocVT == MVT::f128) {
570 LocVT == MVT::f128) {
659 LocVT == MVT::f128) {
838 LocVT = MVT::f128;
939 if (LocVT == MVT::f128 ||
[all...] |
| AArch64GenDAGISel.inc | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 154 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
165 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
171 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
177 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
183 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
189 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
195 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
200 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
205 (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
211 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 159 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
170 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
176 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
182 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
188 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
194 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
200 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
205 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
210 (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
216 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| MachineValueType.h | 54 f128 = 12, // This is a 128 bit floating point value
696 case f128:
804 return MVT::f128;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| X86GenCallingConv.inc | 882 LocVT == MVT::f128) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 95 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
97 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
474 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal);
475 setOperationAction(ISD::FMAXNAN, MVT::f128, Legal);
476 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
477 setOperationAction(ISD::FMINNAN, MVT::f128, Legal);
480 // We have fused multiply-addition for f32 and f64 but not f128.
484 setOperationAction(ISD::FMA, MVT::f128, Legal);
486 setOperationAction(ISD::FMA, MVT::f128, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 68 case MVT::f128: return "MVT::f128";
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenTarget.cpp | 64 case MVT::f128: return "MVT::f128";
|
