/external/u-boot/drivers/ddr/fsl/ |
arm_ddr_gen3.c | 129 ddr_out32(&ddr->sdram_cfg_2, 140 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 186 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 188 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 231 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 242 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 244 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
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mpc85xx_ddr_gen3.c | 152 out_be32(&ddr->sdram_cfg_2, 163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); 332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 363 /* 2. Set DINIT in SDRAM_CFG_2*/ 364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); 365 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", 366 in_be32(&ddr->sdram_cfg_2)); 386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 432 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) & [all...] |
mpc85xx_ddr_gen2.c | 70 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 90 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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mpc86xx_ddr.c | 55 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 79 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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fsl_ddr_gen4.c | 217 ddr_out32(&ddr->sdram_cfg_2, 228 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 281 ddr_out32(&ddr->sdram_cfg_2, 331 temp32 = ddr_in32(&ddr->sdram_cfg_2); 333 ddr_out32(&ddr->sdram_cfg_2, temp32); 434 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 466 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 497 temp32 = ddr_in32(&ddr->sdram_cfg_2); 499 ddr_out32(&ddr->sdram_cfg_2, temp32);
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/external/u-boot/board/socrates/ |
sdram.c | 42 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
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/external/u-boot/board/freescale/bsc9132qds/ |
spl_minimal.c | 25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); 45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
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/external/u-boot/board/freescale/mpc8572ds/ |
mpc8572ds.c | 79 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 99 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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/external/u-boot/board/sbc8641d/ |
sbc8641d.c | 114 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; 145 ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
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/external/u-boot/board/freescale/bsc9131rdb/ |
spl_minimal.c | 36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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/external/u-boot/board/sbc8548/ |
ddr.c | 110 out_be32(&ddr->sdram_cfg_2, 0x24401000);
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/external/u-boot/board/freescale/ls1021atwr/ |
ls1021atwr.c | 158 out_be32(&ddr->sdram_cfg_2, 169 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 199 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 201 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 213 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 215 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
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/external/u-boot/board/freescale/mpc8569mds/ |
mpc8569mds.c | 245 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 255 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); 271 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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/external/u-boot/board/freescale/mpc8536ds/ |
mpc8536ds.c | 107 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 127 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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/external/u-boot/board/freescale/mpc8610hpcd/ |
mpc8610hpcd.c | 163 ddr->sdram_cfg_2 = 0x04400010; 184 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
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/external/u-boot/arch/arm/cpu/armv7/ls102xa/ |
ls102xa_psci.c | 122 setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
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/external/u-boot/board/freescale/ls1021aiot/ |
ls1021aiot.c | 64 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
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/external/u-boot/board/freescale/mpc8641hpcn/ |
mpc8641hpcn.c | 98 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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/external/u-boot/include/ |
fsl_immap.h | 38 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ member in struct:ccsr_ddr
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