/external/u-boot/board/freescale/corenet_ds/ |
p4080ds_ddr.c | 102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/board/freescale/p1_twr/ |
ddr.c | 45 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/board/freescale/bsc9132qds/ |
ddr.c | 36 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 63 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
spl_minimal.c | 39 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
|
/external/u-boot/board/freescale/bsc9131rdb/ |
spl_minimal.c | 46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
|
ddr.c | 37 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/board/freescale/ls1043ardb/ |
ddr.h | 88 .timing_cfg_5 = 0x03401400,
|
/external/u-boot/board/Arcturus/ucp1020/ |
ddr.c | 105 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/board/freescale/p1010rdb/ |
ddr.c | 39 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 66 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/drivers/ddr/fsl/ |
arm_ddr_gen3.c | 108 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
|
fsl_ddr_gen4.c | 160 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
|
mpc85xx_ddr_gen3.c | 131 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
|
ctrl_regs.c | [all...] |
interactive.c | 659 CFG_REGS(timing_cfg_5), 750 CFG_REGS(timing_cfg_5), [all...] |
/external/u-boot/board/freescale/ls1021aiot/ |
ls1021aiot.c | 62 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
|
/external/u-boot/board/freescale/p1_p2_rdb_pc/ |
ddr.c | 237 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
/external/u-boot/include/ |
fsl_immap.h | 51 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ member in struct:ccsr_ddr
|
fsl_ddr_sdram.h | 278 unsigned int timing_cfg_5; member in struct:fsl_ddr_cfg_regs_s
|
/external/u-boot/board/freescale/mpc8569mds/ |
mpc8569mds.c | 252 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
|
/external/u-boot/board/freescale/ls1021atwr/ |
ls1021atwr.c | 154 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
|