1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2005-2006 Atmel Corporation 4 */ 5 #include <common.h> 6 #include <clk.h> 7 #include <dm.h> 8 9 /* 10 * The u-boot networking stack is a little weird. It seems like the 11 * networking core allocates receive buffers up front without any 12 * regard to the hardware that's supposed to actually receive those 13 * packets. 14 * 15 * The MACB receives packets into 128-byte receive buffers, so the 16 * buffers allocated by the core isn't very practical to use. We'll 17 * allocate our own, but we need one such buffer in case a packet 18 * wraps around the DMA ring so that we have to copy it. 19 * 20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 21 * configuration header. This way, the core allocates one RX buffer 22 * and one TX buffer, each of which can hold a ethernet packet of 23 * maximum size. 24 * 25 * For some reason, the networking core unconditionally specifies a 26 * 32-byte packet "alignment" (which really should be called 27 * "padding"). MACB shouldn't need that, but we'll refrain from any 28 * core modifications here... 29 */ 30 31 #include <net.h> 32 #ifndef CONFIG_DM_ETH 33 #include <netdev.h> 34 #endif 35 #include <malloc.h> 36 #include <miiphy.h> 37 38 #include <linux/mii.h> 39 #include <asm/io.h> 40 #include <asm/dma-mapping.h> 41 #include <asm/arch/clk.h> 42 #include <linux/errno.h> 43 44 #include "macb.h" 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 #define MACB_RX_BUFFER_SIZE 4096 49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 50 #define MACB_TX_RING_SIZE 16 51 #define MACB_TX_TIMEOUT 1000 52 #define MACB_AUTONEG_TIMEOUT 5000000 53 54 #ifdef CONFIG_MACB_ZYNQ 55 /* INCR4 AHB bursts */ 56 #define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004 57 /* Use full configured addressable space (8 Kb) */ 58 #define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300 59 /* Use full configured addressable space (4 Kb) */ 60 #define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400 61 /* Set RXBUF with use of 128 byte */ 62 #define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000 63 #define MACB_ZYNQ_GEM_DMACR_INIT \ 64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \ 65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \ 66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \ 67 MACB_ZYNQ_GEM_DMACR_RXBUF) 68 #endif 69 70 struct macb_dma_desc { 71 u32 addr; 72 u32 ctrl; 73 }; 74 75 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 76 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 77 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 78 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 79 80 #define RXADDR_USED 0x00000001 81 #define RXADDR_WRAP 0x00000002 82 83 #define RXBUF_FRMLEN_MASK 0x00000fff 84 #define RXBUF_FRAME_START 0x00004000 85 #define RXBUF_FRAME_END 0x00008000 86 #define RXBUF_TYPEID_MATCH 0x00400000 87 #define RXBUF_ADDR4_MATCH 0x00800000 88 #define RXBUF_ADDR3_MATCH 0x01000000 89 #define RXBUF_ADDR2_MATCH 0x02000000 90 #define RXBUF_ADDR1_MATCH 0x04000000 91 #define RXBUF_BROADCAST 0x80000000 92 93 #define TXBUF_FRMLEN_MASK 0x000007ff 94 #define TXBUF_FRAME_END 0x00008000 95 #define TXBUF_NOCRC 0x00010000 96 #define TXBUF_EXHAUSTED 0x08000000 97 #define TXBUF_UNDERRUN 0x10000000 98 #define TXBUF_MAXRETRY 0x20000000 99 #define TXBUF_WRAP 0x40000000 100 #define TXBUF_USED 0x80000000 101 102 struct macb_device { 103 void *regs; 104 105 unsigned int rx_tail; 106 unsigned int tx_head; 107 unsigned int tx_tail; 108 unsigned int next_rx_tail; 109 bool wrapped; 110 111 void *rx_buffer; 112 void *tx_buffer; 113 struct macb_dma_desc *rx_ring; 114 struct macb_dma_desc *tx_ring; 115 116 unsigned long rx_buffer_dma; 117 unsigned long rx_ring_dma; 118 unsigned long tx_ring_dma; 119 120 struct macb_dma_desc *dummy_desc; 121 unsigned long dummy_desc_dma; 122 123 const struct device *dev; 124 #ifndef CONFIG_DM_ETH 125 struct eth_device netdev; 126 #endif 127 unsigned short phy_addr; 128 struct mii_dev *bus; 129 #ifdef CONFIG_PHYLIB 130 struct phy_device *phydev; 131 #endif 132 133 #ifdef CONFIG_DM_ETH 134 #ifdef CONFIG_CLK 135 unsigned long pclk_rate; 136 #endif 137 phy_interface_t phy_interface; 138 #endif 139 }; 140 #ifndef CONFIG_DM_ETH 141 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 142 #endif 143 144 static int macb_is_gem(struct macb_device *macb) 145 { 146 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 147 } 148 149 #ifndef cpu_is_sama5d2 150 #define cpu_is_sama5d2() 0 151 #endif 152 153 #ifndef cpu_is_sama5d4 154 #define cpu_is_sama5d4() 0 155 #endif 156 157 static int gem_is_gigabit_capable(struct macb_device *macb) 158 { 159 /* 160 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 161 * configured to support only 10/100. 162 */ 163 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 164 } 165 166 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 167 { 168 unsigned long netctl; 169 unsigned long netstat; 170 unsigned long frame; 171 172 netctl = macb_readl(macb, NCR); 173 netctl |= MACB_BIT(MPE); 174 macb_writel(macb, NCR, netctl); 175 176 frame = (MACB_BF(SOF, 1) 177 | MACB_BF(RW, 1) 178 | MACB_BF(PHYA, macb->phy_addr) 179 | MACB_BF(REGA, reg) 180 | MACB_BF(CODE, 2) 181 | MACB_BF(DATA, value)); 182 macb_writel(macb, MAN, frame); 183 184 do { 185 netstat = macb_readl(macb, NSR); 186 } while (!(netstat & MACB_BIT(IDLE))); 187 188 netctl = macb_readl(macb, NCR); 189 netctl &= ~MACB_BIT(MPE); 190 macb_writel(macb, NCR, netctl); 191 } 192 193 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 194 { 195 unsigned long netctl; 196 unsigned long netstat; 197 unsigned long frame; 198 199 netctl = macb_readl(macb, NCR); 200 netctl |= MACB_BIT(MPE); 201 macb_writel(macb, NCR, netctl); 202 203 frame = (MACB_BF(SOF, 1) 204 | MACB_BF(RW, 2) 205 | MACB_BF(PHYA, macb->phy_addr) 206 | MACB_BF(REGA, reg) 207 | MACB_BF(CODE, 2)); 208 macb_writel(macb, MAN, frame); 209 210 do { 211 netstat = macb_readl(macb, NSR); 212 } while (!(netstat & MACB_BIT(IDLE))); 213 214 frame = macb_readl(macb, MAN); 215 216 netctl = macb_readl(macb, NCR); 217 netctl &= ~MACB_BIT(MPE); 218 macb_writel(macb, NCR, netctl); 219 220 return MACB_BFEXT(DATA, frame); 221 } 222 223 void __weak arch_get_mdio_control(const char *name) 224 { 225 return; 226 } 227 228 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 229 230 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) 231 { 232 u16 value = 0; 233 #ifdef CONFIG_DM_ETH 234 struct udevice *dev = eth_get_dev_by_name(bus->name); 235 struct macb_device *macb = dev_get_priv(dev); 236 #else 237 struct eth_device *dev = eth_get_dev_by_name(bus->name); 238 struct macb_device *macb = to_macb(dev); 239 #endif 240 241 if (macb->phy_addr != phy_adr) 242 return -1; 243 244 arch_get_mdio_control(bus->name); 245 value = macb_mdio_read(macb, reg); 246 247 return value; 248 } 249 250 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, 251 u16 value) 252 { 253 #ifdef CONFIG_DM_ETH 254 struct udevice *dev = eth_get_dev_by_name(bus->name); 255 struct macb_device *macb = dev_get_priv(dev); 256 #else 257 struct eth_device *dev = eth_get_dev_by_name(bus->name); 258 struct macb_device *macb = to_macb(dev); 259 #endif 260 261 if (macb->phy_addr != phy_adr) 262 return -1; 263 264 arch_get_mdio_control(bus->name); 265 macb_mdio_write(macb, reg, value); 266 267 return 0; 268 } 269 #endif 270 271 #define RX 1 272 #define TX 0 273 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 274 { 275 if (rx) 276 invalidate_dcache_range(macb->rx_ring_dma, 277 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE, 278 PKTALIGN)); 279 else 280 invalidate_dcache_range(macb->tx_ring_dma, 281 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE, 282 PKTALIGN)); 283 } 284 285 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 286 { 287 if (rx) 288 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 289 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN)); 290 else 291 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 292 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN)); 293 } 294 295 static inline void macb_flush_rx_buffer(struct macb_device *macb) 296 { 297 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 298 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 299 } 300 301 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 302 { 303 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 304 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 305 } 306 307 #if defined(CONFIG_CMD_NET) 308 309 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 310 int length) 311 { 312 unsigned long paddr, ctrl; 313 unsigned int tx_head = macb->tx_head; 314 int i; 315 316 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 317 318 ctrl = length & TXBUF_FRMLEN_MASK; 319 ctrl |= TXBUF_FRAME_END; 320 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 321 ctrl |= TXBUF_WRAP; 322 macb->tx_head = 0; 323 } else { 324 macb->tx_head++; 325 } 326 327 macb->tx_ring[tx_head].ctrl = ctrl; 328 macb->tx_ring[tx_head].addr = paddr; 329 barrier(); 330 macb_flush_ring_desc(macb, TX); 331 /* Do we need check paddr and length is dcache line aligned? */ 332 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 333 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 334 335 /* 336 * I guess this is necessary because the networking core may 337 * re-use the transmit buffer as soon as we return... 338 */ 339 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 340 barrier(); 341 macb_invalidate_ring_desc(macb, TX); 342 ctrl = macb->tx_ring[tx_head].ctrl; 343 if (ctrl & TXBUF_USED) 344 break; 345 udelay(1); 346 } 347 348 dma_unmap_single(packet, length, paddr); 349 350 if (i <= MACB_TX_TIMEOUT) { 351 if (ctrl & TXBUF_UNDERRUN) 352 printf("%s: TX underrun\n", name); 353 if (ctrl & TXBUF_EXHAUSTED) 354 printf("%s: TX buffers exhausted in mid frame\n", name); 355 } else { 356 printf("%s: TX timeout\n", name); 357 } 358 359 /* No one cares anyway */ 360 return 0; 361 } 362 363 static void reclaim_rx_buffers(struct macb_device *macb, 364 unsigned int new_tail) 365 { 366 unsigned int i; 367 368 i = macb->rx_tail; 369 370 macb_invalidate_ring_desc(macb, RX); 371 while (i > new_tail) { 372 macb->rx_ring[i].addr &= ~RXADDR_USED; 373 i++; 374 if (i > MACB_RX_RING_SIZE) 375 i = 0; 376 } 377 378 while (i < new_tail) { 379 macb->rx_ring[i].addr &= ~RXADDR_USED; 380 i++; 381 } 382 383 barrier(); 384 macb_flush_ring_desc(macb, RX); 385 macb->rx_tail = new_tail; 386 } 387 388 static int _macb_recv(struct macb_device *macb, uchar **packetp) 389 { 390 unsigned int next_rx_tail = macb->next_rx_tail; 391 void *buffer; 392 int length; 393 u32 status; 394 395 macb->wrapped = false; 396 for (;;) { 397 macb_invalidate_ring_desc(macb, RX); 398 399 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED)) 400 return -EAGAIN; 401 402 status = macb->rx_ring[next_rx_tail].ctrl; 403 if (status & RXBUF_FRAME_START) { 404 if (next_rx_tail != macb->rx_tail) 405 reclaim_rx_buffers(macb, next_rx_tail); 406 macb->wrapped = false; 407 } 408 409 if (status & RXBUF_FRAME_END) { 410 buffer = macb->rx_buffer + 128 * macb->rx_tail; 411 length = status & RXBUF_FRMLEN_MASK; 412 413 macb_invalidate_rx_buffer(macb); 414 if (macb->wrapped) { 415 unsigned int headlen, taillen; 416 417 headlen = 128 * (MACB_RX_RING_SIZE 418 - macb->rx_tail); 419 taillen = length - headlen; 420 memcpy((void *)net_rx_packets[0], 421 buffer, headlen); 422 memcpy((void *)net_rx_packets[0] + headlen, 423 macb->rx_buffer, taillen); 424 *packetp = (void *)net_rx_packets[0]; 425 } else { 426 *packetp = buffer; 427 } 428 429 if (++next_rx_tail >= MACB_RX_RING_SIZE) 430 next_rx_tail = 0; 431 macb->next_rx_tail = next_rx_tail; 432 return length; 433 } else { 434 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 435 macb->wrapped = true; 436 next_rx_tail = 0; 437 } 438 } 439 barrier(); 440 } 441 } 442 443 static void macb_phy_reset(struct macb_device *macb, const char *name) 444 { 445 int i; 446 u16 status, adv; 447 448 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 449 macb_mdio_write(macb, MII_ADVERTISE, adv); 450 printf("%s: Starting autonegotiation...\n", name); 451 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 452 | BMCR_ANRESTART)); 453 454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 455 status = macb_mdio_read(macb, MII_BMSR); 456 if (status & BMSR_ANEGCOMPLETE) 457 break; 458 udelay(100); 459 } 460 461 if (status & BMSR_ANEGCOMPLETE) 462 printf("%s: Autonegotiation complete\n", name); 463 else 464 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 465 name, status); 466 } 467 468 static int macb_phy_find(struct macb_device *macb, const char *name) 469 { 470 int i; 471 u16 phy_id; 472 473 /* Search for PHY... */ 474 for (i = 0; i < 32; i++) { 475 macb->phy_addr = i; 476 phy_id = macb_mdio_read(macb, MII_PHYSID1); 477 if (phy_id != 0xffff) { 478 printf("%s: PHY present at %d\n", name, i); 479 return 0; 480 } 481 } 482 483 /* PHY isn't up to snuff */ 484 printf("%s: PHY not found\n", name); 485 486 return -ENODEV; 487 } 488 489 /** 490 * macb_linkspd_cb - Linkspeed change callback function 491 * @regs: Base Register of MACB devices 492 * @speed: Linkspeed 493 * Returns 0 when operation success and negative errno number 494 * when operation failed. 495 */ 496 int __weak macb_linkspd_cb(void *regs, unsigned int speed) 497 { 498 return 0; 499 } 500 501 #ifdef CONFIG_DM_ETH 502 static int macb_phy_init(struct udevice *dev, const char *name) 503 #else 504 static int macb_phy_init(struct macb_device *macb, const char *name) 505 #endif 506 { 507 #ifdef CONFIG_DM_ETH 508 struct macb_device *macb = dev_get_priv(dev); 509 #endif 510 u32 ncfgr; 511 u16 phy_id, status, adv, lpa; 512 int media, speed, duplex; 513 int ret; 514 int i; 515 516 arch_get_mdio_control(name); 517 /* Auto-detect phy_addr */ 518 ret = macb_phy_find(macb, name); 519 if (ret) 520 return ret; 521 522 /* Check if the PHY is up to snuff... */ 523 phy_id = macb_mdio_read(macb, MII_PHYSID1); 524 if (phy_id == 0xffff) { 525 printf("%s: No PHY present\n", name); 526 return -ENODEV; 527 } 528 529 #ifdef CONFIG_PHYLIB 530 #ifdef CONFIG_DM_ETH 531 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, 532 macb->phy_interface); 533 #else 534 /* need to consider other phy interface mode */ 535 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 536 PHY_INTERFACE_MODE_RGMII); 537 #endif 538 if (!macb->phydev) { 539 printf("phy_connect failed\n"); 540 return -ENODEV; 541 } 542 543 phy_config(macb->phydev); 544 #endif 545 546 status = macb_mdio_read(macb, MII_BMSR); 547 if (!(status & BMSR_LSTATUS)) { 548 /* Try to re-negotiate if we don't have link already. */ 549 macb_phy_reset(macb, name); 550 551 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 552 status = macb_mdio_read(macb, MII_BMSR); 553 if (status & BMSR_LSTATUS) 554 break; 555 udelay(100); 556 } 557 } 558 559 if (!(status & BMSR_LSTATUS)) { 560 printf("%s: link down (status: 0x%04x)\n", 561 name, status); 562 return -ENETDOWN; 563 } 564 565 /* First check for GMAC and that it is GiB capable */ 566 if (gem_is_gigabit_capable(macb)) { 567 lpa = macb_mdio_read(macb, MII_STAT1000); 568 569 if (lpa & (LPA_1000FULL | LPA_1000HALF)) { 570 duplex = ((lpa & LPA_1000FULL) ? 1 : 0); 571 572 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 573 name, 574 duplex ? "full" : "half", 575 lpa); 576 577 ncfgr = macb_readl(macb, NCFGR); 578 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 579 ncfgr |= GEM_BIT(GBE); 580 581 if (duplex) 582 ncfgr |= MACB_BIT(FD); 583 584 macb_writel(macb, NCFGR, ncfgr); 585 586 ret = macb_linkspd_cb(macb->regs, _1000BASET); 587 if (ret) 588 return ret; 589 590 return 0; 591 } 592 } 593 594 /* fall back for EMAC checking */ 595 adv = macb_mdio_read(macb, MII_ADVERTISE); 596 lpa = macb_mdio_read(macb, MII_LPA); 597 media = mii_nway_result(lpa & adv); 598 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 599 ? 1 : 0); 600 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 601 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 602 name, 603 speed ? "100" : "10", 604 duplex ? "full" : "half", 605 lpa); 606 607 ncfgr = macb_readl(macb, NCFGR); 608 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 609 if (speed) { 610 ncfgr |= MACB_BIT(SPD); 611 ret = macb_linkspd_cb(macb->regs, _100BASET); 612 } else { 613 ret = macb_linkspd_cb(macb->regs, _10BASET); 614 } 615 616 if (ret) 617 return ret; 618 619 if (duplex) 620 ncfgr |= MACB_BIT(FD); 621 macb_writel(macb, NCFGR, ncfgr); 622 623 return 0; 624 } 625 626 static int gmac_init_multi_queues(struct macb_device *macb) 627 { 628 int i, num_queues = 1; 629 u32 queue_mask; 630 631 /* bit 0 is never set but queue 0 always exists */ 632 queue_mask = gem_readl(macb, DCFG6) & 0xff; 633 queue_mask |= 0x1; 634 635 for (i = 1; i < MACB_MAX_QUEUES; i++) 636 if (queue_mask & (1 << i)) 637 num_queues++; 638 639 macb->dummy_desc->ctrl = TXBUF_USED; 640 macb->dummy_desc->addr = 0; 641 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 642 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); 643 644 for (i = 1; i < num_queues; i++) 645 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 646 647 return 0; 648 } 649 650 #ifdef CONFIG_DM_ETH 651 static int _macb_init(struct udevice *dev, const char *name) 652 #else 653 static int _macb_init(struct macb_device *macb, const char *name) 654 #endif 655 { 656 #ifdef CONFIG_DM_ETH 657 struct macb_device *macb = dev_get_priv(dev); 658 #endif 659 unsigned long paddr; 660 int ret; 661 int i; 662 663 /* 664 * macb_halt should have been called at some point before now, 665 * so we'll assume the controller is idle. 666 */ 667 668 /* initialize DMA descriptors */ 669 paddr = macb->rx_buffer_dma; 670 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 671 if (i == (MACB_RX_RING_SIZE - 1)) 672 paddr |= RXADDR_WRAP; 673 macb->rx_ring[i].addr = paddr; 674 macb->rx_ring[i].ctrl = 0; 675 paddr += 128; 676 } 677 macb_flush_ring_desc(macb, RX); 678 macb_flush_rx_buffer(macb); 679 680 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 681 macb->tx_ring[i].addr = 0; 682 if (i == (MACB_TX_RING_SIZE - 1)) 683 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 684 else 685 macb->tx_ring[i].ctrl = TXBUF_USED; 686 } 687 macb_flush_ring_desc(macb, TX); 688 689 macb->rx_tail = 0; 690 macb->tx_head = 0; 691 macb->tx_tail = 0; 692 macb->next_rx_tail = 0; 693 694 #ifdef CONFIG_MACB_ZYNQ 695 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); 696 #endif 697 698 macb_writel(macb, RBQP, macb->rx_ring_dma); 699 macb_writel(macb, TBQP, macb->tx_ring_dma); 700 701 if (macb_is_gem(macb)) { 702 /* Check the multi queue and initialize the queue for tx */ 703 gmac_init_multi_queues(macb); 704 705 /* 706 * When the GMAC IP with GE feature, this bit is used to 707 * select interface between RGMII and GMII. 708 * When the GMAC IP without GE feature, this bit is used 709 * to select interface between RMII and MII. 710 */ 711 #ifdef CONFIG_DM_ETH 712 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) || 713 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII)) 714 gem_writel(macb, UR, GEM_BIT(RGMII)); 715 else 716 gem_writel(macb, UR, 0); 717 #else 718 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 719 gem_writel(macb, UR, GEM_BIT(RGMII)); 720 #else 721 gem_writel(macb, UR, 0); 722 #endif 723 #endif 724 } else { 725 /* choose RMII or MII mode. This depends on the board */ 726 #ifdef CONFIG_DM_ETH 727 #ifdef CONFIG_AT91FAMILY 728 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 729 macb_writel(macb, USRIO, 730 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 731 } else { 732 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 733 } 734 #else 735 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 736 macb_writel(macb, USRIO, 0); 737 else 738 macb_writel(macb, USRIO, MACB_BIT(MII)); 739 #endif 740 #else 741 #ifdef CONFIG_RMII 742 #ifdef CONFIG_AT91FAMILY 743 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 744 #else 745 macb_writel(macb, USRIO, 0); 746 #endif 747 #else 748 #ifdef CONFIG_AT91FAMILY 749 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 750 #else 751 macb_writel(macb, USRIO, MACB_BIT(MII)); 752 #endif 753 #endif /* CONFIG_RMII */ 754 #endif 755 } 756 757 #ifdef CONFIG_DM_ETH 758 ret = macb_phy_init(dev, name); 759 #else 760 ret = macb_phy_init(macb, name); 761 #endif 762 if (ret) 763 return ret; 764 765 /* Enable TX and RX */ 766 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 767 768 return 0; 769 } 770 771 static void _macb_halt(struct macb_device *macb) 772 { 773 u32 ncr, tsr; 774 775 /* Halt the controller and wait for any ongoing transmission to end. */ 776 ncr = macb_readl(macb, NCR); 777 ncr |= MACB_BIT(THALT); 778 macb_writel(macb, NCR, ncr); 779 780 do { 781 tsr = macb_readl(macb, TSR); 782 } while (tsr & MACB_BIT(TGO)); 783 784 /* Disable TX and RX, and clear statistics */ 785 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 786 } 787 788 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 789 { 790 u32 hwaddr_bottom; 791 u16 hwaddr_top; 792 793 /* set hardware address */ 794 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 795 enetaddr[2] << 16 | enetaddr[3] << 24; 796 macb_writel(macb, SA1B, hwaddr_bottom); 797 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 798 macb_writel(macb, SA1T, hwaddr_top); 799 return 0; 800 } 801 802 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 803 { 804 u32 config; 805 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 806 unsigned long macb_hz = macb->pclk_rate; 807 #else 808 unsigned long macb_hz = get_macb_pclk_rate(id); 809 #endif 810 811 if (macb_hz < 20000000) 812 config = MACB_BF(CLK, MACB_CLK_DIV8); 813 else if (macb_hz < 40000000) 814 config = MACB_BF(CLK, MACB_CLK_DIV16); 815 else if (macb_hz < 80000000) 816 config = MACB_BF(CLK, MACB_CLK_DIV32); 817 else 818 config = MACB_BF(CLK, MACB_CLK_DIV64); 819 820 return config; 821 } 822 823 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 824 { 825 u32 config; 826 827 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 828 unsigned long macb_hz = macb->pclk_rate; 829 #else 830 unsigned long macb_hz = get_macb_pclk_rate(id); 831 #endif 832 833 if (macb_hz < 20000000) 834 config = GEM_BF(CLK, GEM_CLK_DIV8); 835 else if (macb_hz < 40000000) 836 config = GEM_BF(CLK, GEM_CLK_DIV16); 837 else if (macb_hz < 80000000) 838 config = GEM_BF(CLK, GEM_CLK_DIV32); 839 else if (macb_hz < 120000000) 840 config = GEM_BF(CLK, GEM_CLK_DIV48); 841 else if (macb_hz < 160000000) 842 config = GEM_BF(CLK, GEM_CLK_DIV64); 843 else 844 config = GEM_BF(CLK, GEM_CLK_DIV96); 845 846 return config; 847 } 848 849 /* 850 * Get the DMA bus width field of the network configuration register that we 851 * should program. We find the width from decoding the design configuration 852 * register to find the maximum supported data bus width. 853 */ 854 static u32 macb_dbw(struct macb_device *macb) 855 { 856 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 857 case 4: 858 return GEM_BF(DBW, GEM_DBW128); 859 case 2: 860 return GEM_BF(DBW, GEM_DBW64); 861 case 1: 862 default: 863 return GEM_BF(DBW, GEM_DBW32); 864 } 865 } 866 867 static void _macb_eth_initialize(struct macb_device *macb) 868 { 869 int id = 0; /* This is not used by functions we call */ 870 u32 ncfgr; 871 872 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 873 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 874 &macb->rx_buffer_dma); 875 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 876 &macb->rx_ring_dma); 877 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 878 &macb->tx_ring_dma); 879 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 880 &macb->dummy_desc_dma); 881 882 /* 883 * Do some basic initialization so that we at least can talk 884 * to the PHY 885 */ 886 if (macb_is_gem(macb)) { 887 ncfgr = gem_mdc_clk_div(id, macb); 888 ncfgr |= macb_dbw(macb); 889 } else { 890 ncfgr = macb_mdc_clk_div(id, macb); 891 } 892 893 macb_writel(macb, NCFGR, ncfgr); 894 } 895 896 #ifndef CONFIG_DM_ETH 897 static int macb_send(struct eth_device *netdev, void *packet, int length) 898 { 899 struct macb_device *macb = to_macb(netdev); 900 901 return _macb_send(macb, netdev->name, packet, length); 902 } 903 904 static int macb_recv(struct eth_device *netdev) 905 { 906 struct macb_device *macb = to_macb(netdev); 907 uchar *packet; 908 int length; 909 910 macb->wrapped = false; 911 for (;;) { 912 macb->next_rx_tail = macb->rx_tail; 913 length = _macb_recv(macb, &packet); 914 if (length >= 0) { 915 net_process_received_packet(packet, length); 916 reclaim_rx_buffers(macb, macb->next_rx_tail); 917 } else { 918 return length; 919 } 920 } 921 } 922 923 static int macb_init(struct eth_device *netdev, bd_t *bd) 924 { 925 struct macb_device *macb = to_macb(netdev); 926 927 return _macb_init(macb, netdev->name); 928 } 929 930 static void macb_halt(struct eth_device *netdev) 931 { 932 struct macb_device *macb = to_macb(netdev); 933 934 return _macb_halt(macb); 935 } 936 937 static int macb_write_hwaddr(struct eth_device *netdev) 938 { 939 struct macb_device *macb = to_macb(netdev); 940 941 return _macb_write_hwaddr(macb, netdev->enetaddr); 942 } 943 944 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 945 { 946 struct macb_device *macb; 947 struct eth_device *netdev; 948 949 macb = malloc(sizeof(struct macb_device)); 950 if (!macb) { 951 printf("Error: Failed to allocate memory for MACB%d\n", id); 952 return -1; 953 } 954 memset(macb, 0, sizeof(struct macb_device)); 955 956 netdev = &macb->netdev; 957 958 macb->regs = regs; 959 macb->phy_addr = phy_addr; 960 961 if (macb_is_gem(macb)) 962 sprintf(netdev->name, "gmac%d", id); 963 else 964 sprintf(netdev->name, "macb%d", id); 965 966 netdev->init = macb_init; 967 netdev->halt = macb_halt; 968 netdev->send = macb_send; 969 netdev->recv = macb_recv; 970 netdev->write_hwaddr = macb_write_hwaddr; 971 972 _macb_eth_initialize(macb); 973 974 eth_register(netdev); 975 976 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 977 int retval; 978 struct mii_dev *mdiodev = mdio_alloc(); 979 if (!mdiodev) 980 return -ENOMEM; 981 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); 982 mdiodev->read = macb_miiphy_read; 983 mdiodev->write = macb_miiphy_write; 984 985 retval = mdio_register(mdiodev); 986 if (retval < 0) 987 return retval; 988 macb->bus = miiphy_get_dev_by_name(netdev->name); 989 #endif 990 return 0; 991 } 992 #endif /* !CONFIG_DM_ETH */ 993 994 #ifdef CONFIG_DM_ETH 995 996 static int macb_start(struct udevice *dev) 997 { 998 return _macb_init(dev, dev->name); 999 } 1000 1001 static int macb_send(struct udevice *dev, void *packet, int length) 1002 { 1003 struct macb_device *macb = dev_get_priv(dev); 1004 1005 return _macb_send(macb, dev->name, packet, length); 1006 } 1007 1008 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 1009 { 1010 struct macb_device *macb = dev_get_priv(dev); 1011 1012 macb->next_rx_tail = macb->rx_tail; 1013 macb->wrapped = false; 1014 1015 return _macb_recv(macb, packetp); 1016 } 1017 1018 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 1019 { 1020 struct macb_device *macb = dev_get_priv(dev); 1021 1022 reclaim_rx_buffers(macb, macb->next_rx_tail); 1023 1024 return 0; 1025 } 1026 1027 static void macb_stop(struct udevice *dev) 1028 { 1029 struct macb_device *macb = dev_get_priv(dev); 1030 1031 _macb_halt(macb); 1032 } 1033 1034 static int macb_write_hwaddr(struct udevice *dev) 1035 { 1036 struct eth_pdata *plat = dev_get_platdata(dev); 1037 struct macb_device *macb = dev_get_priv(dev); 1038 1039 return _macb_write_hwaddr(macb, plat->enetaddr); 1040 } 1041 1042 static const struct eth_ops macb_eth_ops = { 1043 .start = macb_start, 1044 .send = macb_send, 1045 .recv = macb_recv, 1046 .stop = macb_stop, 1047 .free_pkt = macb_free_pkt, 1048 .write_hwaddr = macb_write_hwaddr, 1049 }; 1050 1051 #ifdef CONFIG_CLK 1052 static int macb_enable_clk(struct udevice *dev) 1053 { 1054 struct macb_device *macb = dev_get_priv(dev); 1055 struct clk clk; 1056 ulong clk_rate; 1057 int ret; 1058 1059 ret = clk_get_by_index(dev, 0, &clk); 1060 if (ret) 1061 return -EINVAL; 1062 1063 /* 1064 * Zynq clock driver didn't support for enable or disable 1065 * clock. Hence, clk_enable() didn't apply for Zynq 1066 */ 1067 #ifndef CONFIG_MACB_ZYNQ 1068 ret = clk_enable(&clk); 1069 if (ret) 1070 return ret; 1071 #endif 1072 1073 clk_rate = clk_get_rate(&clk); 1074 if (!clk_rate) 1075 return -EINVAL; 1076 1077 macb->pclk_rate = clk_rate; 1078 1079 return 0; 1080 } 1081 #endif 1082 1083 static int macb_eth_probe(struct udevice *dev) 1084 { 1085 struct eth_pdata *pdata = dev_get_platdata(dev); 1086 struct macb_device *macb = dev_get_priv(dev); 1087 const char *phy_mode; 1088 __maybe_unused int ret; 1089 1090 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1091 NULL); 1092 if (phy_mode) 1093 macb->phy_interface = phy_get_interface_by_name(phy_mode); 1094 if (macb->phy_interface == -1) { 1095 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1096 return -EINVAL; 1097 } 1098 1099 macb->regs = (void *)pdata->iobase; 1100 1101 #ifdef CONFIG_CLK 1102 ret = macb_enable_clk(dev); 1103 if (ret) 1104 return ret; 1105 #endif 1106 1107 _macb_eth_initialize(macb); 1108 1109 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1110 macb->bus = mdio_alloc(); 1111 if (!macb->bus) 1112 return -ENOMEM; 1113 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); 1114 macb->bus->read = macb_miiphy_read; 1115 macb->bus->write = macb_miiphy_write; 1116 1117 ret = mdio_register(macb->bus); 1118 if (ret < 0) 1119 return ret; 1120 macb->bus = miiphy_get_dev_by_name(dev->name); 1121 #endif 1122 1123 return 0; 1124 } 1125 1126 static int macb_eth_remove(struct udevice *dev) 1127 { 1128 struct macb_device *macb = dev_get_priv(dev); 1129 1130 #ifdef CONFIG_PHYLIB 1131 free(macb->phydev); 1132 #endif 1133 mdio_unregister(macb->bus); 1134 mdio_free(macb->bus); 1135 1136 return 0; 1137 } 1138 1139 /** 1140 * macb_late_eth_ofdata_to_platdata 1141 * @dev: udevice struct 1142 * Returns 0 when operation success and negative errno number 1143 * when operation failed. 1144 */ 1145 int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev) 1146 { 1147 return 0; 1148 } 1149 1150 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1151 { 1152 struct eth_pdata *pdata = dev_get_platdata(dev); 1153 1154 pdata->iobase = devfdt_get_addr(dev); 1155 1156 return macb_late_eth_ofdata_to_platdata(dev); 1157 } 1158 1159 static const struct udevice_id macb_eth_ids[] = { 1160 { .compatible = "cdns,macb" }, 1161 { .compatible = "cdns,at91sam9260-macb" }, 1162 { .compatible = "atmel,sama5d2-gem" }, 1163 { .compatible = "atmel,sama5d3-gem" }, 1164 { .compatible = "atmel,sama5d4-gem" }, 1165 { .compatible = "cdns,zynq-gem" }, 1166 { } 1167 }; 1168 1169 U_BOOT_DRIVER(eth_macb) = { 1170 .name = "eth_macb", 1171 .id = UCLASS_ETH, 1172 .of_match = macb_eth_ids, 1173 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1174 .probe = macb_eth_probe, 1175 .remove = macb_eth_remove, 1176 .ops = &macb_eth_ops, 1177 .priv_auto_alloc_size = sizeof(struct macb_device), 1178 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1179 }; 1180 #endif 1181 1182 #endif 1183
