| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| GVN.cpp | 790 // If the load and store are to the exact same address, they should have been
[all...] |
| LoopStrengthReduce.cpp | 559 /// ExtractSymbol - If S involves the addition of a GlobalValue address,
587 /// specified value as an address.
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/ProfileData/ |
| InstrProf.h | 417 uint64_t Address = 0;
425 // A map from function runtime address to function name MD5 hash.
447 /// the section base address. The decompression will be delayed
484 /// Map a function address to its name's MD5 hash. This interface
491 uint64_t getFunctionHashFromAddress(uint64_t Address);
494 /// address in the object file. If an error occurs, return
526 Address = BaseAddr;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | 751 const Value *Address = DI.getAddress();
752 if (!Address || isa<UndefValue>(Address)) {
760 auto AI = dyn_cast<AllocaInst>(Address);
767 MIRBuilder.buildDirectDbgValue(getOrCreateVReg(*Address),
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| SelectionDAGISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/ |
| DWARFContext.cpp | 693 // Assume all compile units have the same address byte size.
707 // Assume all compile units have the same address byte size.
729 // There's a "bug" in the DWARFv3 standard with respect to the target address
731 // of its container, FDEs have fields with size being "target address size",
877 DWARFCompileUnit *DWARFContext::getCompileUnitForAddress(uint64_t Address)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 82 // All possible address modes.
83 class Address {
99 // Innocuous defaults for our address.
100 Address() { Base.Reg = 0; }
173 bool computeAddress(const Value *Obj, Address &Addr);
174 bool computeCallAddress(const Value *V, Address &Addr);
175 void simplifyAddress(Address &Addr);
179 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
181 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
183 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 67 typedef struct Address {
80 // Innocuous defaults for our address.
81 Address()
85 } Address;
158 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
161 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
162 bool PPCComputeAddress(const Value *Obj, Address &Addr);
163 void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
319 // Given a value Obj, create an Address object Addr that represents its
320 // address. Return false if we can't handle it
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 304 // emit a separate ADD node for the global address offset instead of folding
305 // it in the global address node. Later peephole optimisations may choose to
428 // vastart just stores the address of the VarArgsFrameIndex slot into the
482 // Return the value of the return address register, marking it an implicit
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 417 /// Address-mode matching performs shift-of-and to and-of-shift
556 // If the other operand is a TLS address, we should fold it instead.
563 // if the block also has an access to a second TLS address this will save
660 /// Return true if call address is a load and it can be
732 /// Also try moving call address load from outside callseq_start to just
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 874 Value *Address, AvailableValue &Res) {
887 if (Address && LI->isAtomic() <= DepSI->isAtomic()) {
889 analyzeLoadFromClobberingStore(LI->getType(), Address, DepSI, DL);
905 if (DepLI != LI && Address && LI->isAtomic() <= DepLI->isAtomic()) {
907 analyzeLoadFromClobberingLoad(LI->getType(), Address, DepLI, DL);
919 if (Address && !LI->isAtomic()) {
920 int Offset = analyzeLoadFromClobberingMemInst(LI->getType(), Address,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
| Local.cpp | 317 Value *Address = IBI->getAddress();
320 RecursivelyDeleteTriviallyDeadInstructions(Address, TLI);
694 // Zap anything that took the address of DestBB. Not doing this will give the
695 // address an invalid value.
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/sancov/ |
| sancov.cpp | 734 uint64_t Address = AddressOrErr.get();
742 Result.insert(Address);
770 // is defined as the 'address of instruction following __sanitizer_cov
834 // Sanitizer coverage uses the address of the next instruction - 1.
888 // is defined as the 'address of instruction following __sanitizer_cov
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/DebugInfo/DWARF/ |
| DWARFDebugInfoTest.cpp | 88 // Test address forms
219 // Add an address at the end to make sure we can decode this value
239 // Test address forms
380 // Add an address at the end to make sure we can decode this value
389 // DW_FORM_ref_addr are the same as the address type in DWARF32 version 2.
398 // DW_FORM_ref_addr are the same as the address type in DWARF32 version 2.
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX8664Traits.h | 93 // Needed by subclass Address.
190 class Address : public Operand {
191 Address() = default;
194 Address(const Address &) = default;
195 Address(Address &&) = default;
196 Address &operator=(const Address &) = default;
197 Address &operator=(Address &&) = default
[all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkPkg/Include/Protocol/ |
| LegacyBios.h | 42 /// physical address range. It is located on a 16-byte boundary and provides the physical address of the
119 /// The address of an OEM-provided identifier string. The string is null terminated.
124 /// The 32-bit physical address where ACPI RSD PTR is stored within the traditional
137 /// The 32-bit physical address where INT15 E820 data is stored within the traditional
149 /// The 32-bit physical address where the $PIR table is stored in the traditional BIOS.
161 /// The 32-bit physical address where the MP table is stored in the traditional BIOS.
233 /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If
234 /// UmaAddress is a valid address in the shadow RAM, it also indicates that the region
246 /// Start Address of high memory that can be used for permanent allocation. If zero,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 45 class Address {
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
142 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
143 bool computeCallAddress(const Value *V, Address &Addr);
144 bool simplifyAddress(Address &Addr, MVT VT);
145 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
149 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
184 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
186 bool emitStore(MVT VT, unsigned SrcReg, Address Addr
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 52 // All possible address modes, plus some.
53 typedef struct Address {
66 // Innocuous defaults for our address.
67 Address()
71 } Address;
165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
168 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
170 bool ARMComputeAddress(const Value *Obj, Address &Addr);
171 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
173 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 89 // All possible address modes, plus some.
90 struct Address {
103 // Innocuous defaults for our address.
104 Address() {
196 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
199 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
201 bool ARMComputeAddress(const Value *Obj, Address &Addr);
202 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
204 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ |
| Smbios.h | 503 UINT32 Address;
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/Ipf/ |
| SalApi.h | 280 // Virtual address registration
366 UINT64 Address;
|
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Sal.h | 53 /// Virtual address not registered.
234 // memory address is specified
242 // The encoded value of the entity whose physical address is registered
265 // The type of PCI configuration address
270 /// The format of PCI Compatible Address.
281 /// The format of Extended Register Address.
498 UINT64 Address;
|
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
