| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 330 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
394 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
4814 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); local
4821 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); local
6507 int op = (Operands[2]->isImm()) ? 2 : 3; local
[all...] |
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVInstruction.h | 67 bool isSpecConstantOpAllowedOp(Op OC);
106 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVType *TheType,
109 SPIRVInstruction(unsigned TheWordCount, Op TheOC,
113 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVId TheId,
116 SPIRVInstruction(unsigned TheWordCount, Op TheOC,
119 SPIRVInstruction(unsigned TheWordCount, Op TheOC, SPIRVType *TheType,
122 SPIRVInstruction(Op TheOC = OpNop):SPIRVValue(TheOC), BB(NULL){}
182 static SPIRVInstTemplateBase *create(Op TheOC){
189 static SPIRVInstTemplateBase *create(Op TheOC, SPIRVType *TheType,
197 static SPIRVInstTemplateBase *create(Op TheOC, SPIRVType *TheType
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return BitConvertToInteger(Op);
195 SDValue Op = GetSoftenedFloat(N->getOperand(0));
196 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
240 SDValue Op = GetSoftenedFloat(N->getOperand(0));
247 NVT, Op, false, SDLoc(N)).first;
303 SDValue Op = GetSoftenedFloat(N->getOperand(0));
310 NVT, Op, false, SDLoc(N)).first;
328 SDValue Op = GetSoftenedFloat(N->getOperand(0));
335 NVT, Op, false, SDLoc(N)).first
[all...] |
| DAGCombiner.cpp | 83 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
228 bool SimplifyDemandedBits(SDValue Op) {
229 unsigned BitWidth = Op.getScalarValueSizeInBits();
231 return SimplifyDemandedBits(Op, Demanded);
237 bool SimplifyDemandedVectorElts(SDValue Op) {
238 unsigned NumElts = Op.getValueType().getVectorNumElements();
240 return SimplifyDemandedVectorElts(Op, Demanded);
243 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
244 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &Demanded,
263 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace)
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 308 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
709 auto Op = make_unique<PPCOperand>(Token);
710 Op->Tok.Data = Str.data();
711 Op->Tok.Length = Str.size();
712 Op->StartLoc = S;
713 Op->EndLoc = S;
714 Op->IsPPC64 = IsPPC64;
715 return Op;
726 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
727 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| InstrTypes.h | 284 : Instruction(Ty, iType, &Op<0>(), 1, IB) {
285 Op<0>() = V;
288 : Instruction(Ty, iType, &Op<0>(), 1, IAE) {
289 Op<0>() = V;
353 static BinaryOperator *Create(BinaryOps Op, Value *S1, Value *S2,
361 static BinaryOperator *Create(BinaryOps Op, Value *S1, Value *S2,
420 static BinaryOperator *CreateFNegFMF(Value *Op, BinaryOperator *FMFSource,
422 Value *Zero = ConstantFP::getNegativeZero(Op->getType());
423 return CreateWithCopiedFlags(Instruction::FSub, Zero, Op, FMFSource);
518 static BinaryOperator *CreateNeg(Value *Op, const Twine &Name = ""
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 325 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
746 auto Op = make_unique<PPCOperand>(Token);
747 Op->Tok.Data = Str.data();
748 Op->Tok.Length = Str.size();
749 Op->StartLoc = S;
750 Op->EndLoc = S;
751 Op->IsPPC64 = IsPPC64;
752 return Op;
763 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
764 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 434 static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op,
454 Op.setReg(NewReg);
462 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
477 unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB,
482 DEBUG(dbgs() << " - for use in "; Op.getParent()->dump());
486 Op.setReg(NewReg);
537 unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
555 Op.setReg(TeeReg);
601 MachineOperand &Op = *Range.begin();
608 return Op;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 469 static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op,
489 Op.setReg(NewReg);
497 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
512 unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB,
517 LLVM_DEBUG(dbgs() << " - for use in "; Op.getParent()->dump());
521 Op.setReg(NewReg);
572 unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
590 Op.setReg(TeeReg);
636 MachineOperand &Op = *Range.begin();
643 return Op;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return BitConvertToInteger(Op);
192 SDValue Op = GetSoftenedFloat(N->getOperand(0));
193 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
237 SDValue Op = GetSoftenedFloat(N->getOperand(0));
244 NVT, Op, false, SDLoc(N)).first;
300 SDValue Op = GetSoftenedFloat(N->getOperand(0));
307 NVT, Op, false, SDLoc(N)).first;
325 SDValue Op = GetSoftenedFloat(N->getOperand(0));
332 NVT, Op, false, SDLoc(N)).first
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SITypeRewriter.cpp | 148 if (BitCastInst *Op = dyn_cast<BitCastInst>(I.getOperand(0))) {
149 if (Op->getSrcTy() == v4i32) {
150 I.replaceAllUsesWith(Op->getOperand(0));
|
| /external/skia/src/gpu/ |
| GrSWMaskHelper.cpp | 20 static SkBlendMode op_to_mode(SkRegion::Op op) {
31 return modeMap[op];
37 void GrSWMaskHelper::drawRect(const SkRect& rect, const SkMatrix& matrix, SkRegion::Op op, GrAA aa,
40 paint.setBlendMode(op_to_mode(op));
54 void GrSWMaskHelper::drawShape(const GrShape& shape, const SkMatrix& matrix, SkRegion::Op op,
67 if (SkRegion::kReplace_Op == op && 0xFF == alpha) {
71 paint.setBlendMode(op_to_mode(op));
[all...] |
| /external/skqp/src/gpu/ |
| GrSWMaskHelper.cpp | 20 static SkBlendMode op_to_mode(SkRegion::Op op) {
31 return modeMap[op];
37 void GrSWMaskHelper::drawRect(const SkRect& rect, const SkMatrix& matrix, SkRegion::Op op, GrAA aa,
40 paint.setBlendMode(op_to_mode(op));
54 void GrSWMaskHelper::drawShape(const GrShape& shape, const SkMatrix& matrix, SkRegion::Op op,
67 if (SkRegion::kReplace_Op == op && 0xFF == alpha) {
71 paint.setBlendMode(op_to_mode(op));
[all...] |
| /external/spirv-llvm/lib/SPIRV/ |
| SPIRVRegularizeLLVM.cpp | 80 /// Assuming F is a SPIR-V builtin function with op code \param OC.
81 void lowerFuncPtr(Function *F, Op OC);
173 void SPIRVRegularizeLLVM::lowerFuncPtr(Function* F, Op OC) {
194 std::vector<std::pair<Function *, Op>> Work;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 113 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
114 return BitConvertToInteger(Op);
147 SDValue Op = GetSoftenedFloat(N->getOperand(0));
148 return DAG.getNode(ISD::AND, N->getDebugLoc(), NVT, Op, Mask);
165 SDValue Op = GetSoftenedFloat(N->getOperand(0));
171 NVT, &Op, 1, false, N->getDebugLoc());
218 SDValue Op = GetSoftenedFloat(N->getOperand(0));
224 NVT, &Op, 1, false, N->getDebugLoc());
241 SDValue Op = GetSoftenedFloat(N->getOperand(0));
247 NVT, &Op, 1, false, N->getDebugLoc())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineLoadStoreAlloca.cpp | 145 Value *Op = LI.getOperand(0);
150 getOrEnforceKnownAlignment(Op, TD->getPrefTypeAlignment(LI.getType()),TD);
162 if (isa<CastInst>(Op))
174 if (Value *AvailableVal = FindAvailableLoadedValue(Op, LI.getParent(), BBI,6))
178 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(Op)) {
187 Constant::getNullValue(Op->getType()), &LI);
194 if (isa<UndefValue>(Op) ||
195 (isa<ConstantPointerNull>(Op) && LI.getPointerAddressSpace() == 0)) {
200 Constant::getNullValue(Op->getType()), &LI);
205 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Op))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| MachineIRBuilder.h | 306 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
312 /// \pre \p Op must be a generic virtual register with scalar or vector type.
313 /// \pre \p Op must be smaller than \p Res
317 MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op);
323 /// Build and insert \p Res = G_SEXT \p Op
326 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
327 /// high bit of \p Op (i.e. 2s-complement sign extended).
331 /// \pre \p Op must be a generic virtual register with scalar or vector type.
332 /// \pre \p Op must be smaller than \p Res
339 MachineInstrBuilder buildSExt(unsigned Res, unsigned Op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| PhiValues.cpp | 76 for (Value *Op : ComponentPhi->incoming_values()) {
77 if (PHINode *PhiOp = dyn_cast<PHINode>(Op)) {
86 Reachable.insert(Op);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.h | 133 virtual void emitOp(uint8_t Op, const char *Comment = nullptr) = 0;
254 void emitOp(uint8_t Op, const char *Comment = nullptr) override;
271 void emitOp(uint8_t Op, const char *Comment = nullptr) override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| IntrinsicInst.cpp | 39 Value *Op = getArgOperand(0);
40 if (AllowNullOp && !Op)
43 auto *MD = cast<MetadataAsValue>(Op)->getMetadata();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 270 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
272 switch (Op.getOpcode()) {
276 return lowerGlobalAddress(Op, DAG);
278 return lowerBlockAddress(Op, DAG);
280 return lowerConstantPool(Op, DAG);
282 return lowerSELECT(Op, DAG);
284 return lowerVASTART(Op, DAG);
286 return LowerFRAMEADDR(Op, DAG);
288 return LowerRETURNADDR(Op, DAG);
292 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
[all...] |
| /external/tensorflow/tensorflow/compiler/tf2xla/kernels/ |
| unary_ops.cc | 33 class NAME##Op : public XlaOpKernel { \
35 explicit NAME##Op(OpKernelConstruction* ctx) : XlaOpKernel(ctx) {} \
44 REGISTER_XLA_OP(Name(#NAME), NAME##Op);
|
| /external/tensorflow/tensorflow/compiler/xla/service/ |
| algebraic_simplifier.cc | 68 bool IsAll(const HloInstruction* op, int8 value) {
69 switch (op->opcode()) {
71 return IsAll(op->operand(0), value);
73 return op->literal().IsAll(value);
79 // Checks whether `op` is a floating-point constant or broadcast of a constant
83 bool IsAllFpConstantPowerOf2(const HloInstruction* op) {
86 if (!Match(op, m::ConstantEffectiveScalar(&c)) &&
87 !Match(op, m::Broadcast(m::Constant(&c).WithShape(
490 CHECK(Match(add, m::Add(m::Op(&lhs), m::Op(&rhs))))
605 HloInstruction* op; local
626 HloInstruction* op; local
[all...] |
| /external/tensorflow/tensorflow/go/genop/internal/ |
| genop.go | 117 for _, op := range ops.Op {
118 if blacklist[op.Name] {
121 apidef, err := apimap.Get(op.Name)
125 if err := generateFunctionForOp(w, op, apidef); err != nil {
132 func generateFunctionForOp(w io.Writer, op *pb.OpDef, apidef *pb.ApiDef) error {
133 if strings.HasPrefix(op.Name, "_") { // Internal operation
138 for _, a := range op.Attr {
144 for _, a := range op.InputArg {
149 for _, a := range op.OutputArg
[all...] |
| /external/llvm/lib/IR/ |
| Globals.cpp | 233 Op<0>() = InitVal;
251 Op<0>() = InitVal;
278 Op<0>().set(nullptr);
289 Op<0>().set(InitVal);
315 : GlobalValue(Ty, VTy, &Op<0>(), 1, Linkage, Name, AddressSpace) {
316 Op<0>() = Symbol;
|
