| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 96 setOperationAction(ISD::SUB, VecTys[i], Legal);
338 setOperationAction(ISD::SUB, Ty, Legal);
814 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
817 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.h | [all...] |
| SelectionDAGDumper.cpp | 176 case ISD::SUB: return "sub";
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 133 // ADD, SUB overflow.
623 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 172 // ADD, SUB overflow.
484 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
801 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
802 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
839 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
840 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
[all...] |
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 472 // Add/sub (immediate, shifted and extended.)
479 SUB = 0x40000000,
480 SUBS = SUB | AddSubSetFlagsBit
486 V(SUB), \
522 // Add/sub with carry.
532 SBC_w = AddSubWithCarryFixed | SUB,
533 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| /external/libaom/libaom/third_party/x86inc/ |
| x86inc.asm | 368 %macro SUB 2
369 sub %1, %2
457 SUB rsp, stack_size_padded
474 sub rsp, stack_size_padded
563 SUB rsp, stack_size_padded
[all...] |
| /external/libvpx/libvpx/third_party/x86inc/ |
| x86inc.asm | 368 %macro SUB 2
369 sub %1, %2
457 SUB rsp, stack_size_padded
474 sub rsp, stack_size_padded
563 SUB rsp, stack_size_padded
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeSPARC_common.c | 58 sub operation has no side effect. */
59 "sub %i0, 4, %i0\n"
176 #define SUB (OPC1(0x2) | OPC3(0x04))
841 return push_inst(compiler, SUB | D(SLJIT_R1) | S1(TMP_REG2) | S2(SLJIT_R1), DR(SLJIT_R1));
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 519 SUB = ((4U << 3) + 2),
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 199 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
238 // Custom lower Add/Sub/Mul with overflow.
464 // Vector add and sub nodes may conceal a high-half opportunity.
467 setTargetDAGCombine(ISD::SUB);
[all...] |
| /external/libaom/libaom/third_party/libyuv/source/ |
| x86inc.asm | 243 %macro SUB 2
244 sub %1, %2
347 SUB rsp, (xmm_regs_used-6)*16+16
802 sub %1, -128
811 %macro sub 2
816 sub %1, %2
819 sub %1, %2
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 198 /// Combined add and sub on an FP vector.
218 // Integer add/sub with unsigned saturation.
222 // Integer add/sub with signed saturation.
229 /// Integer horizontal add/sub.
233 /// Floating point horizontal add/sub.
342 ADD, SUB, ADC, SBB, SMUL,
861 /// register EAX to i16 by referencing its sub-register AX.
[all...] |