| /external/spirv-llvm/lib/SPIRV/ |
| OCLUtil.cpp | 595 ArrayRef<Type*> ArgTypes, std::string &MangledName) {
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| LoopSimplify.cpp | 417 SplitLandingPadPredecessors(Exit, ArrayRef<BasicBlock*>(&LoopBlocks[0],
|
| /external/swiftshader/third_party/LLVM/unittests/ADT/ |
| APIntTest.cpp | 257 EXPECT_EQ(APInt(32, uint64_t(1)), APInt(32, ArrayRef<uint64_t>(1)));
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 22 #include "llvm/ADT/ArrayRef.h"
211 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| CGSCCPassManager.cpp | 11 #include "llvm/ADT/ArrayRef.h"
611 N, *CallTarget, [&](ArrayRef<SCC *> MergedSCCs) {
|
| MemorySSAUpdater.cpp | 501 BasicBlock *Old, BasicBlock *New, ArrayRef<BasicBlock *> Preds) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 17 #include "llvm/ADT/ArrayRef.h"
398 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
|
| MachineRegisterInfo.cpp | 639 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
|
| VirtRegMap.cpp | 423 ArrayRef<MachineInstr *> Srcs,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/CodeView/ |
| TypeRecordMapping.cpp | 265 ArrayRef<VFTableSlotKind> Slots = Record.getSlots();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/MCJIT/ |
| MCJIT.cpp | 507 GenericValue MCJIT::runFunction(Function *F, ArrayRef<GenericValue> ArgValues) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/Orc/ |
| OrcMCJITReplacement.h | 17 #include "llvm/ADT/ArrayRef.h"
368 ArrayRef<GenericValue> ArgValues) override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| ConstantFold.cpp | [all...] |
| DataLayout.cpp | 780 ArrayRef<Value *> Indices) const {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/LTO/ |
| LTOCodeGenerator.cpp | 553 bool LTOCodeGenerator::compileOptimized(ArrayRef<raw_pwrite_stream *> Out) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 445 ArrayRef<MCCFIInstruction> Instrs) const override {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetTransformInfo.cpp | 340 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args ) {
|
| GCNSchedStrategy.cpp | 147 ArrayRef<unsigned> Pressure = RPTracker.getRegSetPressureAtPos();
|
| SIISelLowering.h | 185 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 402 ArrayRef<MachineOperand> Cond,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 16 #include "llvm/ADT/ArrayRef.h"
72 ArrayRef<uint8_t> Bytes, uint64_t Address,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 246 ArrayRef<MachineOperand> Cond,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 19 #include "llvm/ADT/ArrayRef.h"
651 ArrayRef<OperandSpecifier> operands;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCContract.cpp | 317 createCallInst(Value *Func, ArrayRef<Value *> Args, const Twine &NameStr,
|
