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Searched
refs:BIT0
(Results
51 - 75
of
257
) sorted by null
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/device/linaro/bootloader/edk2/SecurityPkg/Include/Guid/
PhysicalPresenceData.h
73
#define FLAG_NO_PPI_PROVISION
BIT0
/device/linaro/bootloader/edk2/SecurityPkg/Include/Library/
TcgPpVendorLib.h
32
#define TCG_BIOS_TPM_MANAGEMENT_FLAG_NO_PPI_PROVISION
BIT0
/device/linaro/bootloader/edk2/ShellPkg/Include/Protocol/
EfiShellInterface.h
39
ARG_IS_QUOTED =
BIT0
,
/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/
SafeString.c
131
ASSERT (((UINTN) String &
BIT0
) == 0);
193
ASSERT (((UINTN) Destination &
BIT0
) == 0);
194
ASSERT (((UINTN) Source &
BIT0
) == 0);
278
ASSERT (((UINTN) Destination &
BIT0
) == 0);
279
ASSERT (((UINTN) Source &
BIT0
) == 0);
373
ASSERT (((UINTN) Destination &
BIT0
) == 0);
374
ASSERT (((UINTN) Source &
BIT0
) == 0);
476
ASSERT (((UINTN) Destination &
BIT0
) == 0);
477
ASSERT (((UINTN) Source &
BIT0
) == 0);
[
all
...]
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
17
#undef
BIT0
53
#define
BIT0
0x00000001U
meminit_utils.c
61
msk = (byte_lane &
BIT0
) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8);
62
tempD = (byte_lane &
BIT0
) ? ((pi_count / HALF_CLK) << 20) : ((pi_count / HALF_CLK) << 8);
71
reg = (byte_lane &
BIT0
) ? (B1DLLPICODER0) : (B0DLLPICODER0);
84
msk |= (byte_lane &
BIT0
) ? (BIT5) : (BIT2);
90
msk |= (byte_lane &
BIT0
) ? (BIT11) : (BIT8);
128
tempD >>= (byte_lane &
BIT0
) ? (20) : (8);
137
reg = (byte_lane &
BIT0
) ? (B1DLLPICODER0) : (B0DLLPICODER0);
170
reg = (byte_lane &
BIT0
) ? (B1RXDQSPICODE) : (B0RXDQSPICODE);
172
msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
BIT0
);
205
reg = (byte_lane &
BIT0
) ? (B1RXDQSPICODE) : (B0RXDQSPICODE);
[
all
...]
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
CommonIncludes.h
50
#ifndef
BIT0
116
#define
BIT0
0x00000001
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
AhciMode.h
24
#define EFI_AHCI_GHC_RESET
BIT0
98
#define EFI_AHCI_PORT_IS_DHRS
BIT0
121
#define EFI_AHCI_PORT_CMD_ST
BIT0
141
#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 |
BIT0
)
144
#define EFI_AHCI_PORT_TFD_ERR
BIT0
163
#define EFI_AHCI_PORT_SERR_RDIE
BIT0
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
XhciReg.h
142
#define XHC_USBCMD_RUN
BIT0
// Run/Stop
147
#define XHC_USBSTS_HALT
BIT0
// Host Controller Halted
159
#define XHC_CRCR_RCS
BIT0
// Ring Cycle State
166
#define XHC_PORTSC_CCS
BIT0
// Current Connect Status
183
#define XHC_HUB_PORTSC_CCS
BIT0
// Hub's Current Connect Status
193
#define XHC_IMAN_IP
BIT0
// Interrupt Pending
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
XhciReg.h
57
#define XHC_USBCMD_RUN
BIT0
// Run/Stop
62
#define XHC_USBSTS_HALT
BIT0
// Host Controller Halted
74
#define XHC_CRCR_RCS
BIT0
// Ring Cycle State
81
#define XHC_PORTSC_CCS
BIT0
// Current Connect Status
98
#define XHC_HUB_PORTSC_CCS
BIT0
// Hub's Current Connect Status
109
#define XHC_IMAN_IP
BIT0
// Interrupt Pending
/device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/
OpalAhciMode.h
37
#define EFI_AHCI_GHC_RESET
BIT0
91
#define EFI_AHCI_PORT_IS_DHRS
BIT0
114
#define EFI_AHCI_PORT_CMD_ST
BIT0
134
#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 |
BIT0
)
137
#define EFI_AHCI_PORT_TFD_ERR
BIT0
156
#define EFI_AHCI_PORT_SERR_RDIE
BIT0
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
150
#define TXSTATUS_DEF
BIT0
// Packet tx was deferred
165
#define IRQCFG_IRQ_TYPE
BIT0
// IRQ Buffer type
200
#define HWCFG_SRST
BIT0
// Software Reset bit (SC)
207
#define MPTCTRL_READY
BIT0
// Device ready indicator
229
#define PHYSTS_EXT_CAP
BIT0
// Extended Capabilities Register capability
305
#define TXCFG_STOP_TX
BIT0
// Stop the transmitter
335
#define MII_ACC_MII_BUSY
BIT0
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/
IsaFloppy.h
194
#define SELECT_DRV
BIT0
222
#define MSR_DAB
BIT0
255
#define CCR_DRC (
BIT0
| BIT1)
366
#define STS0_US0
BIT0
407
#define STS1_MA
BIT0
433
#define STS2_MD
BIT0
454
#define STS3_US0
BIT0
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/
DwUfsHcDxe.h
92
#define UFS_HC_HCE_EN
BIT0
93
#define UFS_HC_HCS_DP
BIT0
100
#define UFS_HC_CAP_NUTRS (
BIT0
| BIT1 | BIT2 | BIT3 | BIT4)
101
#define UFS_HC_UTMRLRSR
BIT0
102
#define UFS_HC_UTRLRSR
BIT0
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
Acpi20.h
204
#define EFI_ACPI_2_0_LEGACY_DEVICES
BIT0
211
#define EFI_ACPI_2_0_WBINVD
BIT0
250
#define EFI_ACPI_2_0_S4BIOS_F
BIT0
271
#define EFI_ACPI_2_0_PCAT_COMPAT
BIT0
306
#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED
BIT0
Acpi30.h
230
#define EFI_ACPI_3_0_LEGACY_DEVICES
BIT0
240
#define EFI_ACPI_3_0_WBINVD
BIT0
285
#define EFI_ACPI_3_0_S4BIOS_F
BIT0
316
#define EFI_ACPI_3_0_PCAT_COMPAT
BIT0
351
#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED
BIT0
478
#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE
BIT0
/device/linaro/bootloader/edk2/OvmfPkg/QemuVideoDxe/
VbeShim.c
131
//
bit0
in each nibble is Read Enable
134
PciWrite8 (Pam1Address, Pam1 | (BIT1 |
BIT0
));
160
VbeInfo->Capabilities =
BIT0
; // DAC can be switched into 8-bit mode
194
//
bit0
: mode supported by present hardware configuration
201
VbeModeInfo->ModeAttr = BIT7 | BIT5 | BIT4 | BIT3 | BIT1 |
BIT0
;
204
//
bit0
: exists
208
VbeModeInfo->WindowAAttr = BIT2 | BIT1 |
BIT0
;
264
// Clear Write Enable (bit1), keep Read Enable (
bit0
) set
266
PciWrite8 (Pam1Address, (Pam1 & ~BIT1) |
BIT0
);
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/
SDController.c
191
if (ErrorCode &
BIT0
) {
358
Data |=
BIT0
;
363
Data &= ~
BIT0
;
488
}while ((TimeOut2-- > 0) && (Data &
BIT0
));
618
//
BIT0
- DMA Enable
622
Data |= BIT4 |
BIT0
;
625
Data |=
BIT0
;
627
Data &= ~(BIT4 |
BIT0
);
676
Data = (CommandIndex << 8) |
BIT0
| BIT1 | BIT4| BIT3;
681
Data = (CommandIndex << 8) |
BIT0
| BIT3;
[
all
...]
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
74
#define MCI_POWER_ON (BIT1 |
BIT0
)
83
#define MCI_STATUS_CMD_CMDCRCFAIL
BIT0
132
#define MCI_DATACTL_ENABLE
BIT0
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
44
#define B_MASTER_MODE
BIT0
76
#define I2C_INTR_RX_UNDER
BIT0
138
#define I2C_INTR_RX_UNDER
BIT0
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/
UsbMass.h
46
#define USB_IS_BULK_ENDPOINT(Attribute) (((Attribute) & (
BIT0
| BIT1)) == USB_ENDPOINT_BULK)
47
#define USB_IS_INTERRUPT_ENDPOINT(Attribute) (((Attribute) & (
BIT0
| BIT1)) == USB_ENDPOINT_INTERRUPT)
/device/linaro/bootloader/edk2/OptionRomPkg/AtapiPassThruDxe/
AtapiPassThru.h
73
#define IDE_PRIMARY_OPERATING_MODE
BIT0
216
#define AMNF_ERR
BIT0
///< Address Mark Not Found
223
#define ILI_ERR
BIT0
///< Illegal Length Indication
233
#define HS0
BIT0
250
#define ERR
BIT0
///< Error
251
#define CHECK
BIT0
///< Check bit for ATAPI Status Reg
263
#define DMA
BIT0
270
#define CoD
BIT0
[
all
...]
/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/
PeCoffExtraActionLib.c
36
return (BOOLEAN) (((Dr7 >> (RegisterIndex * 2)) & (
BIT0
| BIT1)) == (
BIT0
| BIT1));
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
PchRegs.h
45
#ifndef
BIT0
46
#define
BIT0
0x0001
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/
IgdOpRegion.h
71
#define HD_MBOX1
BIT0
94
#define ALS_ENABLE
BIT0
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