| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 290 void Assembler::cbz(const Register& rt, int64_t imm19) {
291 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
295 void Assembler::cbz(const Register& rt, Label* label) {
298 cbz(rt, static_cast<int>(offset));
302 void Assembler::cbnz(const Register& rt, int64_t imm19) {
303 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
[all...] |
| /cts/tests/sensor/src/android/hardware/cts/ |
| SensorManagerStaticTest.java | 271 float [] Rt;
275 Rt = mat9T(mat9VRot(rotv)); // from world frame to phone frame
276 //Rt = mat9I();
283 float [] gmb = mat9Mul(Rt, gm); // do not care about right most column
290 float [] n = mat9Mul(Rr, Rt);
294 i, mat9ToStr(mat9T(Rt)), mat9ToStr(Rr)),
|
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 488 Assembler::Rt(xzr));
524 instr->preceding()->Rt() == xzr.code());
935 bool result = instr->IsLdrLiteralX() && (instr->Rt() == kZeroRegCode);
[all...] |
| simulator-arm64.cc | 1505 unsigned rt = instr->Rt(); local
1858 unsigned rt = instr->Rt(); local
2016 unsigned rt = instr->Rt(); local
2095 unsigned rt = instr->Rt(); local
4531 int rt = instr->Rt(); local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| Thumb2SizeReduction.cpp | 437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
442 assert(isARMLowRegister(Rt));
455 .addReg(Rt, IsStore ? 0 : RegState::Define);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| Thumb2SizeReduction.cpp | 467 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
472 assert(isARMLowRegister(Rt));
485 .addReg(Rt, IsStore ? 0 : RegState::Define);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 224 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
227 assert(Ws == Rt.width());
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
231 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
[all...] |
| HexagonBitSimplify.cpp | 532 case S2_storerf_io: // memh(Rs32+#s11:1)=Rt.H32
533 case S2_pstorerft_io: // if (Pv4) memh(Rs32+#u6:1)=Rt.H32
534 case S2_pstorerff_io: // if (!Pv4) memh(Rs32+#u6:1)=Rt.H32
535 case S4_pstorerftnew_io: // if (Pv4.new) memh(Rs32+#u6:1)=Rt.H32
536 case S4_pstorerffnew_io: // if (!Pv4.new) memh(Rs32+#u6:1)=Rt.H32
537 case S2_storerf_pi: // memh(Rx32++#s4:1)=Rt.H32
538 case S2_pstorerft_pi: // if (Pv4) memh(Rx32++#s4:1)=Rt.H32
539 case S2_pstorerff_pi: // if (!Pv4) memh(Rx32++#s4:1)=Rt.H32
540 case S2_pstorerftnew_pi: // if (Pv4.new) memh(Rx32++#s4:1)=Rt.H32
541 case S2_pstorerffnew_pi: // if (!Pv4.new) memh(Rx32++#s4:1)=Rt.H3
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| diagnostics.s | 231 @ Out of order Rt/Rt2 operands for ldrexd/strexd
287 @ Out of order Rt/Rt2 operands for ldrd
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.h | 482 // Dm = Rt:Rt2
486 // Qd[Index] = Rt
494 // Rt = Qm[Index]
498 // Rt:Rt2 = Dm
502 // Rt = Sn
516 // Sn = Rt
746 bool IsByte, IValueT Rt, IValueT Address);
754 void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
759 void emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, IValueT Rt,
764 // size, l=IsLoad, nnnn=Rn (as defined by OpAddress), and tttt=Rt
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| diagnostics.s | 328 @ Out of order Rt/Rt2 operands for ldrexd/strexd
402 @ Out of order Rt/Rt2 operands for ldrd/strd
431 @ CHECK-ERRORS: error: Rt must be even-numbered
434 @ CHECK-ERRORS: error: Rt must be even-numbered
459 @ CHECK-ERRORS: error: Rt can't be R14
462 @ CHECK-ERRORS: error: Rt can't be R14
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 290 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
293 assert(Ws == Rt.width());
294 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
297 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
[all...] |
| HexagonBitSimplify.cpp | 583 case S2_storerf_io: // memh(Rs32+#s11:1)=Rt.H32
584 case S2_pstorerft_io: // if (Pv4) memh(Rs32+#u6:1)=Rt.H32
585 case S2_pstorerff_io: // if (!Pv4) memh(Rs32+#u6:1)=Rt.H32
586 case S4_pstorerftnew_io: // if (Pv4.new) memh(Rs32+#u6:1)=Rt.H32
587 case S4_pstorerffnew_io: // if (!Pv4.new) memh(Rs32+#u6:1)=Rt.H32
588 case S2_storerf_pi: // memh(Rx32++#s4:1)=Rt.H32
589 case S2_pstorerft_pi: // if (Pv4) memh(Rx32++#s4:1)=Rt.H32
590 case S2_pstorerff_pi: // if (!Pv4) memh(Rx32++#s4:1)=Rt.H32
591 case S2_pstorerftnew_pi: // if (Pv4.new) memh(Rx32++#s4:1)=Rt.H32
592 case S2_pstorerffnew_pi: // if (!Pv4.new) memh(Rx32++#s4:1)=Rt.H3
[all...] |
| HexagonSplitDouble.cpp | 377 unsigned Rt = MI->getOperand(2).getReg();
378 return profit(Rs) + profit(Rt);
[all...] |
| /external/pdfium/third_party/lcms/src/ |
| cmspcs.c | 500 deltaC,deltah,dc,t,g,dh,rh,rc,rt,bfd; local
539 rt = rh*rc;
541 bfd = sqrt(Sqr(deltaL)+Sqr(deltaC/dc)+Sqr(deltah/dh)+(rt*(deltaC/dc)*(deltah/dh)));
647 cmsFloat64Number Rt = -sin(2 * RADIANS(delta_ro)) * Rc;
652 Rt*(delta_C/(Sc * Kc)) * (delta_H / (Sh * Kh)));
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 300 @ Out of order Rt/Rt2 operands for ldrexd/strexd
374 @ Out of order Rt/Rt2 operands for ldrd
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
