/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 330 VSELECT, [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 64 // Implement vselect in terms of XOR, AND, OR when blend is not supported 163 case ISD::VSELECT: 217 if (Node->getOpcode() == ISD::VSELECT) 266 // Implement VSELECT in terms of XOR, AND, OR
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LegalizeIntegerTypes.cpp | 67 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 492 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), 771 case ISD::VSELECT: [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 355 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 356 /// change the condition type in order to match the VSELECT node using a 358 VSELECT, [all...] |
BasicTTIImpl.h | 488 ISD = ISD::VSELECT; [all...] |
SelectionDAG.h | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 398 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 399 /// change the condition type in order to match the VSELECT node using a 401 VSELECT, [all...] |
BasicTTIImpl.h | 715 ISD = ISD::VSELECT; [all...] |
SelectionDAG.h | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT); 98 setTargetDAGCombine(ISD::VSELECT); 275 setOperationAction(ISD::VSELECT, Ty, Legal); 320 setOperationAction(ISD::VSELECT, Ty, Legal); 660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b) 776 // Transform the DAG into an equivalent VSELECT. 777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 106 setTargetDAGCombine(ISD::VSELECT); 167 setTargetDAGCombine(ISD::VSELECT); 346 setOperationAction(ISD::VSELECT, Ty, Legal); 391 setOperationAction(ISD::VSELECT, Ty, Legal); 590 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b) 706 // Transform the DAG into an equivalent VSELECT. 707 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not 292 case ISD::VSELECT: 689 case ISD::VSELECT: 711 // operands are vectors. Lower this select to VSELECT and implement it [all...] |
LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; 452 case ISD::VSELECT: 590 case ISD::VSELECT: [all...] |
SelectionDAGDumper.cpp | 216 case ISD::VSELECT: return "vselect";
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LegalizeIntegerTypes.cpp | 75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 582 return DAG.getNode(ISD::VSELECT, SDLoc(N), [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorTypes.cpp | 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; 312 // The vselect result and true/value operands needs scalarizing, but it's 478 case ISD::VSELECT: 647 case ISD::VSELECT: [all...] |
LegalizeVectorOps.cpp | 122 /// Implement vselect in terms of XOR, AND, OR when blend is not 351 case ISD::VSELECT: 719 case ISD::VSELECT: 763 // operands are vectors. Lower this select to VSELECT and implement it [all...] |
SelectionDAGDumper.cpp | 257 case ISD::VSELECT: return "vselect"; [all...] |
LegalizeIntegerTypes.cpp | 77 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 578 return DAG.getNode(ISD::VSELECT, SDLoc(N), [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86ISelLowering.cpp | 740 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand) [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 726 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonISelLoweringHVX.cpp | 158 setOperationAction(ISD::VSELECT, T, Custom); [all...] |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 491 setOperationAction(ISD::VSELECT, VT, Expand); 592 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 593 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); 594 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 595 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 596 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 691 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 741 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); [all...] |