| /external/syzkaller/pkg/ifuzz/gen/ |
| gen.go | 375 case v == "rexw_prefix", v == "W1":
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenRegisterInfo.inc | 206 W1 = 186,
[all...] |
| AArch64GenAsmMatcher.inc | 375 return 186; // "w1"
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips32r5_test.cc | 191 vec_registers_.push_back(new mips::VectorRegister(mips::W1));
|
| assembler_mips32r6_test.cc | 204 vec_registers_.push_back(new mips::VectorRegister(mips::W1));
[all...] |
| /external/dng_sdk/source/ |
| dng_color_space.cpp | 216 dng_vector_3 W1 = M * dng_vector_3 (1.0, 1.0, 1.0);
219 real64 s0 = W2 [0] / W1 [0];
220 real64 s1 = W2 [1] / W1 [1];
221 real64 s2 = W2 [2] / W1 [2];
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 659 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
[all...] |
| /external/elfutils/libcpu/ |
| i386_parse.y | 327 else if (strcmp ($5->name, "w1") == 0)
331 else if (strcmp ($5->name, "W1") == 0)
1161 EMIT_SUFFIX (w1);
1162 EMIT_SUFFIX (W1);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonConstPropagation.cpp | [all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 535 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 402 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 454 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 202 vec_registers_.push_back(new mips64::VectorRegister(mips64::W1));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 327 static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
[all...] |
| /external/webrtc/data/voice_engine/stereo_rtp_files/ |
| toggling_stereo_g729_pt18_pt125.rtp | [all...] |
| hrtf_g722_1C_48.rtp | [all...] |
| hrtf_g722_1C_48_jitterT2.rtp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenAsmMatcher.inc | [all...] |
