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      1 /*
      2  * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 
      7 #include <mmio.h>
      8 #include <nic_400.h>
      9 #include <plat_arm.h>
     10 #include <soc_css.h>
     11 #include "juno_def.h"
     12 
     13 
     14 /*******************************************************************************
     15  * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
     16  * assigned to Non-Secure except some for the DMA-330. Assign those back to the
     17  * Non-Secure world as well, otherwise EL1 may end up erroneously generating
     18  * (untranslated) Secure transactions if it turns the SMMU on.
     19  ******************************************************************************/
     20 static void init_mmu401(void)
     21 {
     22 	uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
     23 	reg |= 0x1FF;
     24 	mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
     25 }
     26 
     27 /*******************************************************************************
     28  * Program CSS-NIC400 to allow non-secure access to some CSS regions.
     29  ******************************************************************************/
     30 static void css_init_nic400(void)
     31 {
     32 	/* Note: This is the NIC-400 device on the CSS */
     33 	mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
     34 		NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
     35 		~0);
     36 }
     37 
     38 /*******************************************************************************
     39  * Initialize debug configuration.
     40  ******************************************************************************/
     41 static void init_debug_cfg(void)
     42 {
     43 #if !DEBUG
     44 	/* Set internal drive selection for SPIDEN. */
     45 	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
     46 		1U << SPIDEN_SEL_SET_SHIFT);
     47 
     48 	/* Drive SPIDEN LOW to disable invasive debug of secure state. */
     49 	mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
     50 		1U << SPIDEN_INT_CLR_SHIFT);
     51 #endif
     52 }
     53 
     54 /*******************************************************************************
     55  * Initialize the secure environment.
     56  ******************************************************************************/
     57 void plat_arm_security_setup(void)
     58 {
     59 	/* Initialize debug configuration */
     60 	init_debug_cfg();
     61 	/* Initialize the TrustZone Controller */
     62 	arm_tzc400_setup();
     63 	/* Do ARM CSS internal NIC setup */
     64 	css_init_nic400();
     65 	/* Do ARM CSS SoC security setup */
     66 	soc_css_security_setup();
     67 	/* Initialize the SMMU SSD tables */
     68 	init_mmu401();
     69 }
     70