1 /** @file 2 3 Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 Module Name: 13 VirtualMemory.h 14 15 Abstract: 16 17 Revision History: 18 19 **/ 20 21 #ifndef _VIRTUAL_MEMORY_H_ 22 #define _VIRTUAL_MEMORY_H_ 23 24 #pragma pack(1) 25 26 // 27 // Page Directory Entry 4K 28 // 29 typedef union { 30 struct { 31 UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory 32 UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 33 UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User 34 UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 35 UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 36 UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 37 UINT32 MustBeZero:3; // Must Be Zero 38 UINT32 Available:3; // Available for use by system software 39 UINT32 PageTableBaseAddress:20; // Page Table Base Address 40 } Bits; 41 UINT32 Uint32; 42 } IA32_PAGE_DIRECTORY_ENTRY_4K; 43 44 // 45 // Page Table Entry 4K 46 // 47 typedef union { 48 struct { 49 UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory 50 UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 51 UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User 52 UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 53 UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 54 UINT32 Accessed:1; // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU) 55 UINT32 Dirty:1; // 0 = Not written to (cleared by software), 1 = Written to (set by CPU) 56 UINT32 PAT:1; // 0 = Disable PAT, 1 = Enable PAT 57 UINT32 Global:1; // Ignored 58 UINT32 Available:3; // Available for use by system software 59 UINT32 PageTableBaseAddress:20; // Page Table Base Address 60 } Bits; 61 UINT32 Uint32; 62 } IA32_PAGE_TABLE_ENTRY_4K; 63 64 // 65 // Page Table Entry 4M 66 // 67 typedef union { 68 struct { 69 UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory 70 UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write 71 UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User 72 UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching 73 UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached 74 UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU) 75 UINT32 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page 76 UINT32 MustBe1:1; // Must be 1 77 UINT32 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write 78 UINT32 Available:3; // Available for use by system software 79 UINT32 PAT:1; // 80 UINT32 MustBeZero:9; // Must be zero; 81 UINT32 PageTableBaseAddress:10; // Page Table Base Address 82 } Bits; 83 UINT32 Uint32; 84 } IA32_PAGE_TABLE_ENTRY_4M; 85 86 #pragma pack() 87 88 #endif 89
