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      1 @/*****************************************************************************
      2 @*
      3 @* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
      4 @*
      5 @* Licensed under the Apache License, Version 2.0 (the "License");
      6 @* you may not use this file except in compliance with the License.
      7 @* You may obtain a copy of the License at:
      8 @*
      9 @* http://www.apache.org/licenses/LICENSE-2.0
     10 @*
     11 @* Unless required by applicable law or agreed to in writing, software
     12 @* distributed under the License is distributed on an "AS IS" BASIS,
     13 @* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14 @* See the License for the specific language governing permissions and
     15 @* limitations under the License.
     16 @*
     17 @*****************************************************************************/
     18 @/**
     19 @ *******************************************************************************
     20 @ * @file
     21 @ *  ihevc_itrans_recon_4x4_ttype1.s
     22 @ *
     23 @ * @brief
     24 @ *  contains function definitions for inverse transform  and reconstruction
     25 @ *
     26 @ *
     27 @ * @author
     28 @ *  naveen sr
     29 @ *
     30 @ * @par list of functions:
     31 @ *  - ihevc_itrans_recon_4x4_ttype1()
     32 @ *
     33 @ * @remarks
     34 @ *  none
     35 @ *
     36 @ *******************************************************************************
     37 @ */
     38 
     39 @/* all the functions here are replicated from ihevc_itrans.c and modified to */
     40 @/* include reconstruction */
     41 @
     42 @/**
     43 @ *******************************************************************************
     44 @ *
     45 @ * @brief
     46 @ *  this function performs inverse transform type 1 (dst)  and reconstruction
     47 @ * for 4x4 input block
     48 @ *
     49 @ * @par description:
     50 @ *  performs inverse transform and adds the prediction  data and clips output
     51 @ * to 8 bit
     52 @ *
     53 @ * @param[in] pi2_src
     54 @ *  input 4x4 coefficients
     55 @ *
     56 @ * @param[in] pi2_tmp
     57 @ *  temporary 4x4 buffer for storing inverse
     58 @ *
     59 @ *  transform
     60 @ *  1st stage output
     61 @ *
     62 @ * @param[in] pu1_pred
     63 @ *  prediction 4x4 block
     64 @ *
     65 @ * @param[out] pu1_dst
     66 @ *  output 4x4 block
     67 @ *
     68 @ * @param[in] src_strd
     69 @ *  input stride
     70 @ *
     71 @ * @param[in] pred_strd
     72 @ *  prediction stride
     73 @ *
     74 @ * @param[in] dst_strd
     75 @ *  output stride
     76 @ *
     77 @ * @param[in] zero_cols
     78 @ *  zero columns in pi2_src
     79 @ *
     80 @ * @returns  void
     81 @ *
     82 @ * @remarks
     83 @ *  none
     84 @ *
     85 @ *******************************************************************************
     86 @ */
     87 @void ihevc_itrans_recon_4x4_ttype1(word16 *pi2_src,
     88 @       word16 *pi2_tmp,
     89 @       uword8 *pu1_pred,
     90 @       uword8 *pu1_dst,
     91 @       word32 src_strd,
     92 @       word32 pred_strd,
     93 @       word32 dst_strd,
     94 @       word32 zero_cols)
     95 
     96 @**************variables vs registers*************************
     97 @   r0 => *pi2_src
     98 @   r1 => *pi2_tmp
     99 @   r2 => *pu1_pred
    100 @   r3 => *pu1_dst
    101 @   r4 => src_strd
    102 @   r5 => pred_strd
    103 @   r6 => dst_strd
    104 @   r7 => zero_cols
    105 
    106 .equ    src_strd_offset,    104
    107 .equ    pred_strd_offset,   108
    108 .equ    dst_strd_offset,    112
    109 .equ    zero_cols_offset,   116
    110 
    111 .text
    112 .align 4
    113 
    114 
    115 
    116 
    117 .set shift_stage1_idct ,   7
    118 .set shift_stage2_idct ,   12
    119 
    120 .globl ihevc_itrans_recon_4x4_ttype1_a9q
    121 
    122 .type ihevc_itrans_recon_4x4_ttype1_a9q, %function
    123 
    124 ihevc_itrans_recon_4x4_ttype1_a9q:
    125 
    126     stmfd       sp!, {r4-r12, r14}          @stack stores the values of the arguments
    127     vpush       {d8  -  d15}
    128 
    129     ldr         r4,[sp,#src_strd_offset]    @loading src_strd
    130     ldr         r5,[sp,#pred_strd_offset]   @loading pred_strd
    131     ldr         r6,[sp,#dst_strd_offset]    @loading dst_strd
    132     ldr         r7,[sp,#zero_cols_offset]   @loading zero_cols
    133 
    134     add         r4,r4,r4                    @ src_strd in terms of word16
    135 
    136     mov         r8,#29
    137     mov         r9,#55
    138     mov         r10,#74
    139     mov         r11,#84
    140     vmov.i16    d4[0],r8
    141     vld1.16     d0,[r0],r4                  @loading pi2_src 1st row
    142     vmov.i16    d4[1],r9
    143     vld1.16     d1,[r0],r4                  @loading pi2_src 2nd row
    144     vmov.i16    d4[2],r10
    145     vld1.16     d2,[r0],r4                  @loading pi2_src 3rd row
    146     vmov.i16    d4[3],r11
    147     vld1.16     d3,[r0],r4                  @loading pi2_src 4th row
    148 
    149     @ first stage computation starts
    150     vmull.s16   q3,d1,d4[2]                 @74 * pi2_src[1]
    151     vmlal.s16   q3,d0,d4[0]                 @74 * pi2_src[1] + 29 * pi2_src[0]
    152     vmlal.s16   q3,d3,d4[1]                 @74 * pi2_src[1] + 29 * pi2_src[0] + 55 * pi2_src[3]
    153     vmlal.s16   q3,d2,d4[3]                 @pi2_out[0] = 29* pi2_src[0] + 74 * pi2_src[1] + 84* pi2_src[2] + 55 * pi2_src[3]
    154 
    155     vmull.s16   q4,d1,d4[2]                 @74 * pi2_src[1]
    156     vmlal.s16   q4,d0,d4[1]                 @74 * pi2_src[1] + 55 * pi2_src[0]
    157     vmlsl.s16   q4,d2,d4[0]                 @74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2]
    158     vmlsl.s16   q4,d3,d4[3]                 @pi2_out[1] = 74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2] - 84 * pi2_src[3])
    159 
    160     vmull.s16   q5,d0,d4[2]                 @ 74 * pi2_src[0]
    161     vmlsl.s16   q5,d2,d4[2]                 @ 74 * pi2_src[0] - 74 * pi2_src[2]
    162     vmlal.s16   q5,d3,d4[2]                 @pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
    163 
    164     vmull.s16   q6,d2,d4[1]                 @ 55 * pi2_src[2]
    165     vmlsl.s16   q6,d1,d4[2]                 @ 55 * pi2_src[2] - 74 * pi2_src[1]
    166     vmlsl.s16   q6,d3,d4[0]                 @ - 74 * pi2_src[1] +   55 * pi2_src[2] - 29 * pi2_src[3]
    167     vmlal.s16   q6,d0,d4[3]                 @pi2_out[3] = 84 * pi2_src[0] - 74 * pi2_src[1] + 55 * pi2_src[2] - 29 * pi2_src[3]
    168 
    169     vqrshrn.s32 d14,q3,#shift_stage1_idct   @ (pi2_out[0] + rounding ) >> shift_stage1_idct
    170     vqrshrn.s32 d15,q4,#shift_stage1_idct   @ (pi2_out[1] + rounding ) >> shift_stage1_idct
    171     vqrshrn.s32 d16,q5,#shift_stage1_idct   @ (pi2_out[2] + rounding ) >> shift_stage1_idct
    172     vqrshrn.s32 d17,q6,#shift_stage1_idct   @ (pi2_out[3] + rounding ) >> shift_stage1_idct
    173     vld1.32     d18[0], [r2],r5
    174 
    175     vtrn.16     d14,d15
    176     vtrn.16     d16,d17
    177     vtrn.32     d14,d16
    178     vtrn.32     d15,d17
    179     @ output in d14,d15,d16,d17
    180     @ first stage computation ends
    181 
    182     @ second stage computation starts  :  copy pasting 1st stage
    183     @ register changes
    184     @ d14 - d0
    185     @ d15 - d1
    186     @ d16 - d2
    187     @ d17 - d3
    188     vld1.32     d18[1], [r2],r5
    189     vmull.s16   q3,d15,d4[2]                @74 * pi2_src[1]
    190     vmlal.s16   q3,d14,d4[0]                @74 * pi2_src[1] + 29 * pi2_src[0]
    191     vmlal.s16   q3,d17,d4[1]                @74 * pi2_src[1] + 29 * pi2_src[0] + 55 * pi2_src[3]
    192     vmlal.s16   q3,d16,d4[3]                @pi2_out[0] = 29* pi2_src[0] + 74 * pi2_src[1] + 84* pi2_src[2] + 55 * pi2_src[3]
    193 
    194     vmull.s16   q4,d15,d4[2]                @74 * pi2_src[1]
    195     vmlal.s16   q4,d14,d4[1]                @74 * pi2_src[1] + 55 * pi2_src[0]
    196     vmlsl.s16   q4,d16,d4[0]                @74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2]
    197     vmlsl.s16   q4,d17,d4[3]                @pi2_out[1] = 74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2] - 84 * pi2_src[3])
    198 
    199     vmull.s16   q5,d14,d4[2]                @ 74 * pi2_src[0]
    200     vmlsl.s16   q5,d16,d4[2]                @ 74 * pi2_src[0] - 74 * pi2_src[2]
    201     vmlal.s16   q5,d17,d4[2]                @pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
    202     vld1.32     d19[0], [r2],r5
    203 
    204     vmull.s16   q6,d16,d4[1]                @ 55 * pi2_src[2]
    205     vmlsl.s16   q6,d15,d4[2]                @  - 74 * pi2_src[1] +   55 * pi2_src[2]
    206     vmlsl.s16   q6,d17,d4[0]                @ - 74 * pi2_src[1] +   55 * pi2_src[2] - 29 * pi2_src[3]
    207     vmlal.s16   q6,d14,d4[3]                @pi2_out[3] = 84 * pi2_src[0] - 74 * pi2_src[1] + 55 * pi2_src[2] - 29 * pi2_src[3]
    208 
    209     vqrshrn.s32 d0,q3,#shift_stage2_idct    @ (pi2_out[0] + rounding ) >> shift_stage1_idct
    210     vqrshrn.s32 d1,q4,#shift_stage2_idct    @ (pi2_out[1] + rounding ) >> shift_stage1_idct
    211     vqrshrn.s32 d2,q5,#shift_stage2_idct    @ (pi2_out[2] + rounding ) >> shift_stage1_idct
    212     vqrshrn.s32 d3,q6,#shift_stage2_idct    @ (pi2_out[3] + rounding ) >> shift_stage1_idct
    213     vld1.32     d19[1], [r2],r5
    214     vtrn.16     d0,d1
    215     vtrn.16     d2,d3
    216     vtrn.32     d0,d2
    217     vtrn.32     d1,d3
    218     @ output in d0,d1,d2,d3
    219     @ second stage computation ends
    220 
    221     @ loading pred
    222 
    223     vaddw.u8    q0,q0,d18                   @ pi2_out(16bit) + pu1_pred(8bit)
    224     vqmovun.s16 d0,q0                       @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
    225     vaddw.u8    q1,q1,d19                   @ pi2_out(16bit) + pu1_pred(8bit)
    226     vqmovun.s16 d1,q1                       @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
    227 
    228     @ storing destination
    229     vst1.32     {d0[0]},[r3],r6
    230     vst1.32     {d0[1]},[r3],r6
    231     vst1.32     {d1[0]},[r3],r6
    232     vst1.32     {d1[1]},[r3],r6
    233 
    234     vpop        {d8  -  d15}
    235     ldmfd       sp!,{r4-r12,r15}            @reload the registers from sp
    236 
    237 
    238 
    239 
    240 
    241 
    242 
    243 
    244 
    245