1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/MC/MCInst.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/Support/Endian.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/TargetRegistry.h" 34 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "amdgpu-disassembler" 39 40 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 41 42 43 inline static MCDisassembler::DecodeStatus 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { 45 Inst.addOperand(Opnd); 46 return Opnd.isValid() ? 47 MCDisassembler::Success : 48 MCDisassembler::SoftFail; 49 } 50 51 #define DECODE_OPERAND2(RegClass, DecName) \ 52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \ 53 unsigned Imm, \ 54 uint64_t /*Addr*/, \ 55 const void *Decoder) { \ 56 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 57 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \ 58 } 59 60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) 61 62 DECODE_OPERAND(VGPR_32) 63 DECODE_OPERAND(VS_32) 64 DECODE_OPERAND(VS_64) 65 66 DECODE_OPERAND(VReg_64) 67 DECODE_OPERAND(VReg_96) 68 DECODE_OPERAND(VReg_128) 69 70 DECODE_OPERAND(SReg_32) 71 DECODE_OPERAND(SReg_32_XM0) 72 DECODE_OPERAND(SReg_64) 73 DECODE_OPERAND(SReg_128) 74 DECODE_OPERAND(SReg_256) 75 DECODE_OPERAND(SReg_512) 76 77 #define GET_SUBTARGETINFO_ENUM 78 #include "AMDGPUGenSubtargetInfo.inc" 79 #undef GET_SUBTARGETINFO_ENUM 80 81 #include "AMDGPUGenDisassemblerTables.inc" 82 83 //===----------------------------------------------------------------------===// 84 // 85 //===----------------------------------------------------------------------===// 86 87 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 88 assert(Bytes.size() >= sizeof(T)); 89 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 90 Bytes = Bytes.slice(sizeof(T)); 91 return Res; 92 } 93 94 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 95 MCInst &MI, 96 uint64_t Inst, 97 uint64_t Address) const { 98 assert(MI.getOpcode() == 0); 99 assert(MI.getNumOperands() == 0); 100 MCInst TmpInst; 101 const auto SavedBytes = Bytes; 102 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 103 MI = TmpInst; 104 return MCDisassembler::Success; 105 } 106 Bytes = SavedBytes; 107 return MCDisassembler::Fail; 108 } 109 110 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 111 ArrayRef<uint8_t> Bytes_, 112 uint64_t Address, 113 raw_ostream &WS, 114 raw_ostream &CS) const { 115 CommentStream = &CS; 116 117 // ToDo: AMDGPUDisassembler supports only VI ISA. 118 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA."); 119 120 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 121 Bytes = Bytes_.slice(0, MaxInstBytesNum); 122 123 DecodeStatus Res = MCDisassembler::Fail; 124 do { 125 // ToDo: better to switch encoding length using some bit predicate 126 // but it is unknown yet, so try all we can 127 128 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 129 // encodings 130 if (Bytes.size() >= 8) { 131 const uint64_t QW = eatBytes<uint64_t>(Bytes); 132 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 133 if (Res) break; 134 135 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 136 if (Res) break; 137 } 138 139 // Reinitialize Bytes as DPP64 could have eaten too much 140 Bytes = Bytes_.slice(0, MaxInstBytesNum); 141 142 // Try decode 32-bit instruction 143 if (Bytes.size() < 4) break; 144 const uint32_t DW = eatBytes<uint32_t>(Bytes); 145 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 146 if (Res) break; 147 148 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 149 if (Res) break; 150 151 if (Bytes.size() < 4) break; 152 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 153 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 154 if (Res) break; 155 156 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 157 } while (false); 158 159 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 160 return Res; 161 } 162 163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 164 return getContext().getRegisterInfo()-> 165 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 166 } 167 168 inline 169 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 170 const Twine& ErrMsg) const { 171 *CommentStream << "Error: " + ErrMsg; 172 173 // ToDo: add support for error operands to MCInst.h 174 // return MCOperand::createError(V); 175 return MCOperand(); 176 } 177 178 inline 179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 180 return MCOperand::createReg(RegId); 181 } 182 183 inline 184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 185 unsigned Val) const { 186 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 187 if (Val >= RegCl.getNumRegs()) 188 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 189 ": unknown register " + Twine(Val)); 190 return createRegOperand(RegCl.getRegister(Val)); 191 } 192 193 inline 194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 195 unsigned Val) const { 196 // ToDo: SI/CI have 104 SGPRs, VI - 102 197 // Valery: here we accepting as much as we can, let assembler sort it out 198 int shift = 0; 199 switch (SRegClassID) { 200 case AMDGPU::SGPR_32RegClassID: 201 case AMDGPU::TTMP_32RegClassID: 202 break; 203 case AMDGPU::SGPR_64RegClassID: 204 case AMDGPU::TTMP_64RegClassID: 205 shift = 1; 206 break; 207 case AMDGPU::SGPR_128RegClassID: 208 case AMDGPU::TTMP_128RegClassID: 209 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 210 // this bundle? 211 case AMDGPU::SReg_256RegClassID: 212 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 213 // this bundle? 214 case AMDGPU::SReg_512RegClassID: 215 shift = 2; 216 break; 217 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 218 // this bundle? 219 default: 220 assert(false); 221 break; 222 } 223 if (Val % (1 << shift)) 224 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 225 << ": scalar reg isn't aligned " << Val; 226 return createRegOperand(SRegClassID, Val >> shift); 227 } 228 229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 230 return decodeSrcOp(OPW32, Val); 231 } 232 233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 234 return decodeSrcOp(OPW64, Val); 235 } 236 237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 238 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 239 } 240 241 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 242 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 243 } 244 245 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 246 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 247 } 248 249 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 250 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 251 } 252 253 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 254 // table-gen generated disassembler doesn't care about operand types 255 // leaving only registry class so SSrc_32 operand turns into SReg_32 256 // and therefore we accept immediates and literals here as well 257 return decodeSrcOp(OPW32, Val); 258 } 259 260 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const { 261 // SReg_32_XM0 is SReg_32 without M0 262 return decodeOperand_SReg_32(Val); 263 } 264 265 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 266 // see decodeOperand_SReg_32 comment 267 return decodeSrcOp(OPW64, Val); 268 } 269 270 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 271 return decodeSrcOp(OPW128, Val); 272 } 273 274 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 275 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 276 } 277 278 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 279 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 280 } 281 282 283 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 284 // For now all literal constants are supposed to be unsigned integer 285 // ToDo: deal with signed/unsigned 64-bit integer constants 286 // ToDo: deal with float/double constants 287 if (Bytes.size() < 4) 288 return errOperand(0, "cannot read literal, inst bytes left " + 289 Twine(Bytes.size())); 290 return MCOperand::createImm(eatBytes<uint32_t>(Bytes)); 291 } 292 293 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 294 using namespace AMDGPU::EncValues; 295 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 296 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 297 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 298 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 299 // Cast prevents negative overflow. 300 } 301 302 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { 303 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 304 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 305 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 306 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 307 // literal constant. 308 float V = 0.0f; 309 switch (Imm) { 310 case 240: V = 0.5f; break; 311 case 241: V = -0.5f; break; 312 case 242: V = 1.0f; break; 313 case 243: V = -1.0f; break; 314 case 244: V = 2.0f; break; 315 case 245: V = -2.0f; break; 316 case 246: V = 4.0f; break; 317 case 247: V = -4.0f; break; 318 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) 319 0x3e22f983 : 320 0x3fc45f306dc9c882); 321 default: break; 322 } 323 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); 324 } 325 326 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 327 using namespace AMDGPU; 328 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 329 switch (Width) { 330 default: // fall 331 case OPW32: return VGPR_32RegClassID; 332 case OPW64: return VReg_64RegClassID; 333 case OPW128: return VReg_128RegClassID; 334 } 335 } 336 337 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 338 using namespace AMDGPU; 339 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 340 switch (Width) { 341 default: // fall 342 case OPW32: return SGPR_32RegClassID; 343 case OPW64: return SGPR_64RegClassID; 344 case OPW128: return SGPR_128RegClassID; 345 } 346 } 347 348 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 349 using namespace AMDGPU; 350 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 351 switch (Width) { 352 default: // fall 353 case OPW32: return TTMP_32RegClassID; 354 case OPW64: return TTMP_64RegClassID; 355 case OPW128: return TTMP_128RegClassID; 356 } 357 } 358 359 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 360 using namespace AMDGPU::EncValues; 361 assert(Val < 512); // enum9 362 363 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 364 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 365 } 366 if (Val <= SGPR_MAX) { 367 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 368 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 369 } 370 if (TTMP_MIN <= Val && Val <= TTMP_MAX) { 371 return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN); 372 } 373 374 assert(Width == OPW32 || Width == OPW64); 375 const bool Is32 = (Width == OPW32); 376 377 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 378 return decodeIntImmed(Val); 379 380 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 381 return decodeFPImmed(Is32, Val); 382 383 if (Val == LITERAL_CONST) 384 return decodeLiteralConstant(); 385 386 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); 387 } 388 389 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 390 using namespace AMDGPU; 391 switch (Val) { 392 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 393 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 394 // ToDo: no support for xnack_mask_lo/_hi register 395 case 104: 396 case 105: break; 397 case 106: return createRegOperand(VCC_LO); 398 case 107: return createRegOperand(VCC_HI); 399 case 108: return createRegOperand(TBA_LO); 400 case 109: return createRegOperand(TBA_HI); 401 case 110: return createRegOperand(TMA_LO); 402 case 111: return createRegOperand(TMA_HI); 403 case 124: return createRegOperand(M0); 404 case 126: return createRegOperand(EXEC_LO); 405 case 127: return createRegOperand(EXEC_HI); 406 // ToDo: no support for vccz register 407 case 251: break; 408 // ToDo: no support for execz register 409 case 252: break; 410 case 253: return createRegOperand(SCC); 411 default: break; 412 } 413 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 414 } 415 416 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 417 using namespace AMDGPU; 418 switch (Val) { 419 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 420 case 106: return createRegOperand(VCC); 421 case 108: return createRegOperand(TBA); 422 case 110: return createRegOperand(TMA); 423 case 126: return createRegOperand(EXEC); 424 default: break; 425 } 426 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 427 } 428 429 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 430 const MCSubtargetInfo &STI, 431 MCContext &Ctx) { 432 return new AMDGPUDisassembler(STI, Ctx); 433 } 434 435 extern "C" void LLVMInitializeAMDGPUDisassembler() { 436 TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler); 437 } 438
