| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenMCPseudoLowering.inc | 15 MCInst TmpInst;
17 TmpInst.setOpcode(Mips::AND_V);
20 TmpInst.addOperand(MCOp);
23 TmpInst.addOperand(MCOp);
26 TmpInst.addOperand(MCOp);
27 EmitToStreamer(OutStreamer, TmpInst);
31 MCInst TmpInst;
33 TmpInst.setOpcode(Mips::AND_V);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| ARMGenMCPseudoLowering.inc | 15 MCInst TmpInst;
17 TmpInst.setOpcode(ARM::Bcc);
20 TmpInst.addOperand(MCOp);
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
24 EmitToStreamer(OutStreamer, TmpInst);
28 MCInst TmpInst;
30 TmpInst.setOpcode(ARM::LDMIA_UPD);
33 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFAsmPrinter.cpp | 51 MCInst TmpInst;
52 MCInstLowering.Lower(MI, TmpInst);
53 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 884 MCInst TmpInst;
885 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
887 TmpInst.addOperand(MCOperand::createImm(
889 TmpInst.addOperand(Inst.getOperand(0));
890 TmpInst.addOperand(Inst.getOperand(1));
891 Inst = TmpInst;
896 MCInst TmpInst;
897 TmpInst.setOpcode(PPC::DCBT);
898 TmpInst.addOperand(Inst.getOperand(2));
899 TmpInst.addOperand(Inst.getOperand(0))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 287 MCInst TmpInst;
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
290 TmpInst.addOperand(Reg);
291 TmpInst.addOperand(MCOperand::createExpr(
293 MappedInst = TmpInst;
306 MCInst TmpInst;
308 TmpInst.setOpcode(Hexagon::L2_loadrigp);
309 TmpInst.addOperand(Reg);
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
312 MappedInst = TmpInst;
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 847 MCInst TmpInst;
848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
850 TmpInst.addOperand(MCOperand::createImm(
852 TmpInst.addOperand(Inst.getOperand(0));
853 TmpInst.addOperand(Inst.getOperand(1));
854 Inst = TmpInst;
859 MCInst TmpInst;
860 TmpInst.setOpcode(PPC::DCBT);
861 TmpInst.addOperand(Inst.getOperand(2));
862 TmpInst.addOperand(Inst.getOperand(0))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| ARCAsmPrinter.cpp | 75 MCInst TmpInst;
76 MCInstLowering.Lower(MI, TmpInst);
77 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 342 MCInst TmpInst;
344 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
345 TmpInst.addOperand(Reg);
346 TmpInst.addOperand(MCOperand::createExpr(
348 MappedInst = TmpInst;
358 MCInst TmpInst;
360 TmpInst.setOpcode(Hexagon::L2_loadrigp);
361 TmpInst.addOperand(Reg);
362 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
364 MappedInst = TmpInst;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 148 MCInst TmpInst;
149 TmpInst.setOpcode(Opcode);
150 TmpInst.addOperand(MCOperand::createReg(Reg0));
151 TmpInst.setLoc(IDLoc);
152 getStreamer().EmitInstruction(TmpInst, *STI);
157 MCInst TmpInst;
158 TmpInst.setOpcode(Opcode);
159 TmpInst.addOperand(MCOperand::createReg(Reg0));
160 TmpInst.addOperand(Op1);
161 TmpInst.setLoc(IDLoc)
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 131 MCInst TmpInst;
132 TmpInst.setOpcode(Opcode);
133 TmpInst.addOperand(MCOperand::createReg(Reg0));
134 TmpInst.setLoc(IDLoc);
135 getStreamer().EmitInstruction(TmpInst, *STI);
140 MCInst TmpInst;
141 TmpInst.setOpcode(Opcode);
142 TmpInst.addOperand(MCOperand::createReg(Reg0));
143 TmpInst.addOperand(Op1);
144 TmpInst.setLoc(IDLoc)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 479 MCInst TmpInst;
539 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
542 TmpInst.setOpcode(PPC::LWZ);
549 const MCOperand TR = TmpInst.getOperand(1);
550 const MCOperand PICR = TmpInst.getOperand(0);
553 TmpInst.getOperand(1) =
555 TmpInst.getOperand(0) = TR;
556 TmpInst.getOperand(2) = PICR;
557 EmitToStreamer(*OutStreamer, TmpInst);
559 TmpInst.setOpcode(PPC::ADD4)
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiAsmPrinter.cpp | 177 MCInst TmpInst;
178 MCInstLowering.Lower(MI, TmpInst);
179 TmpInst.setOpcode(Lanai::BT);
180 OutStreamer->EmitInstruction(TmpInst, STI);
194 MCInst TmpInst;
195 MCInstLowering.Lower(MI, TmpInst);
196 OutStreamer->EmitInstruction(TmpInst, STI);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiAsmPrinter.cpp | 176 MCInst TmpInst;
177 MCInstLowering.Lower(MI, TmpInst);
178 TmpInst.setOpcode(Lanai::BT);
179 OutStreamer->EmitInstruction(TmpInst, STI);
193 MCInst TmpInst;
194 MCInstLowering.Lower(MI, TmpInst);
195 OutStreamer->EmitInstruction(TmpInst, STI);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 153 MCInst TmpInst;
154 MCInstLowering.Lower(MI, TmpInst);
155 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 159 MCInst TmpInst;
160 MCInstLowering.Lower(MI, TmpInst);
161 OutStreamer.EmitInstruction(TmpInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFAsmPrinter.cpp | 129 MCInst TmpInst;
130 MCInstLowering.Lower(MI, TmpInst);
131 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 151 MCInst TmpInst;
152 MCInstLowering.Lower(MI, TmpInst);
153 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVAsmPrinter.cpp | 81 MCInst TmpInst;
82 LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
83 EmitToStreamer(*OutStreamer, TmpInst);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 571 MCInst TmpInst;
572 TmpInst.setOpcode(AArch64::MOVIv16b_ns);
573 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
574 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
575 EmitToStreamer(*OutStreamer, TmpInst);
594 MCInst TmpInst;
595 TmpInst.setOpcode(AArch64::BR);
596 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
597 EmitToStreamer(*OutStreamer, TmpInst);
603 MCInst TmpInst;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMCCodeEmitter.cpp | 98 MCInst TmpInst;
112 TmpInst = MCInstBuilder(RISCV::AUIPC)
115 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
120 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
123 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
124 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
|
