1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "SystemZMCTargetDesc.h" 11 #include "InstPrinter/SystemZInstPrinter.h" 12 #include "SystemZMCAsmInfo.h" 13 #include "llvm/MC/MCInstrInfo.h" 14 #include "llvm/MC/MCRegisterInfo.h" 15 #include "llvm/MC/MCStreamer.h" 16 #include "llvm/MC/MCSubtargetInfo.h" 17 #include "llvm/Support/TargetRegistry.h" 18 19 using namespace llvm; 20 21 #define GET_INSTRINFO_MC_DESC 22 #include "SystemZGenInstrInfo.inc" 23 24 #define GET_SUBTARGETINFO_MC_DESC 25 #include "SystemZGenSubtargetInfo.inc" 26 27 #define GET_REGINFO_MC_DESC 28 #include "SystemZGenRegisterInfo.inc" 29 30 const unsigned SystemZMC::GR32Regs[16] = { 31 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 32 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 33 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 34 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L 35 }; 36 37 const unsigned SystemZMC::GRH32Regs[16] = { 38 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 39 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 40 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 41 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H 42 }; 43 44 const unsigned SystemZMC::GR64Regs[16] = { 45 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 46 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, 47 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, 48 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D 49 }; 50 51 const unsigned SystemZMC::GR128Regs[16] = { 52 SystemZ::R0Q, 0, SystemZ::R2Q, 0, 53 SystemZ::R4Q, 0, SystemZ::R6Q, 0, 54 SystemZ::R8Q, 0, SystemZ::R10Q, 0, 55 SystemZ::R12Q, 0, SystemZ::R14Q, 0 56 }; 57 58 const unsigned SystemZMC::FP32Regs[16] = { 59 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 60 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 61 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 62 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S 63 }; 64 65 const unsigned SystemZMC::FP64Regs[16] = { 66 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 67 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 68 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 69 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D 70 }; 71 72 const unsigned SystemZMC::FP128Regs[16] = { 73 SystemZ::F0Q, SystemZ::F1Q, 0, 0, 74 SystemZ::F4Q, SystemZ::F5Q, 0, 0, 75 SystemZ::F8Q, SystemZ::F9Q, 0, 0, 76 SystemZ::F12Q, SystemZ::F13Q, 0, 0 77 }; 78 79 const unsigned SystemZMC::VR32Regs[32] = { 80 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 81 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 82 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 83 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 84 SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, 85 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, 86 SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, 87 SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S 88 }; 89 90 const unsigned SystemZMC::VR64Regs[32] = { 91 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 92 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 93 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 94 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 95 SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, 96 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, 97 SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, 98 SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D 99 }; 100 101 const unsigned SystemZMC::VR128Regs[32] = { 102 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, 103 SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, 104 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, 105 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 106 SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, 107 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, 108 SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, 109 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31 110 }; 111 112 unsigned SystemZMC::getFirstReg(unsigned Reg) { 113 static unsigned Map[SystemZ::NUM_TARGET_REGS]; 114 static bool Initialized = false; 115 if (!Initialized) { 116 for (unsigned I = 0; I < 16; ++I) { 117 Map[GR32Regs[I]] = I; 118 Map[GRH32Regs[I]] = I; 119 Map[GR64Regs[I]] = I; 120 Map[GR128Regs[I]] = I; 121 Map[FP128Regs[I]] = I; 122 } 123 for (unsigned I = 0; I < 32; ++I) { 124 Map[VR32Regs[I]] = I; 125 Map[VR64Regs[I]] = I; 126 Map[VR128Regs[I]] = I; 127 } 128 } 129 assert(Reg < SystemZ::NUM_TARGET_REGS); 130 return Map[Reg]; 131 } 132 133 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 134 const Triple &TT) { 135 MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); 136 MCCFIInstruction Inst = 137 MCCFIInstruction::createDefCfa(nullptr, 138 MRI.getDwarfRegNum(SystemZ::R15D, true), 139 SystemZMC::CFAOffsetFromInitialSP); 140 MAI->addInitialFrameState(Inst); 141 return MAI; 142 } 143 144 static MCInstrInfo *createSystemZMCInstrInfo() { 145 MCInstrInfo *X = new MCInstrInfo(); 146 InitSystemZMCInstrInfo(X); 147 return X; 148 } 149 150 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { 151 MCRegisterInfo *X = new MCRegisterInfo(); 152 InitSystemZMCRegisterInfo(X, SystemZ::R14D); 153 return X; 154 } 155 156 static MCSubtargetInfo * 157 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 158 return createSystemZMCSubtargetInfoImpl(TT, CPU, FS); 159 } 160 161 static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, 162 CodeModel::Model &CM) { 163 // For SystemZ we define the models as follows: 164 // 165 // Small: BRASL can call any function and will use a stub if necessary. 166 // Locally-binding symbols will always be in range of LARL. 167 // 168 // Medium: BRASL can call any function and will use a stub if necessary. 169 // GOT slots and locally-defined text will always be in range 170 // of LARL, but other symbols might not be. 171 // 172 // Large: Equivalent to Medium for now. 173 // 174 // Kernel: Equivalent to Medium for now. 175 // 176 // This means that any PIC module smaller than 4GB meets the 177 // requirements of Small, so Small seems like the best default there. 178 // 179 // All symbols bind locally in a non-PIC module, so the choice is less 180 // obvious. There are two cases: 181 // 182 // - When creating an executable, PLTs and copy relocations allow 183 // us to treat external symbols as part of the executable. 184 // Any executable smaller than 4GB meets the requirements of Small, 185 // so that seems like the best default. 186 // 187 // - When creating JIT code, stubs will be in range of BRASL if the 188 // image is less than 4GB in size. GOT entries will likewise be 189 // in range of LARL. However, the JIT environment has no equivalent 190 // of copy relocs, so locally-binding data symbols might not be in 191 // the range of LARL. We need the Medium model in that case. 192 if (CM == CodeModel::Default) 193 CM = CodeModel::Small; 194 else if (CM == CodeModel::JITDefault) 195 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 196 } 197 198 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, 199 unsigned SyntaxVariant, 200 const MCAsmInfo &MAI, 201 const MCInstrInfo &MII, 202 const MCRegisterInfo &MRI) { 203 return new SystemZInstPrinter(MAI, MII, MRI); 204 } 205 206 extern "C" void LLVMInitializeSystemZTargetMC() { 207 // Register the MCAsmInfo. 208 TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, 209 createSystemZMCAsmInfo); 210 211 // Register the adjustCodeGenOpts. 212 TargetRegistry::registerMCAdjustCodeGenOpts(TheSystemZTarget, 213 adjustCodeGenOpts); 214 215 // Register the MCCodeEmitter. 216 TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget, 217 createSystemZMCCodeEmitter); 218 219 // Register the MCInstrInfo. 220 TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, 221 createSystemZMCInstrInfo); 222 223 // Register the MCRegisterInfo. 224 TargetRegistry::RegisterMCRegInfo(TheSystemZTarget, 225 createSystemZMCRegisterInfo); 226 227 // Register the MCSubtargetInfo. 228 TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, 229 createSystemZMCSubtargetInfo); 230 231 // Register the MCAsmBackend. 232 TargetRegistry::RegisterMCAsmBackend(TheSystemZTarget, 233 createSystemZMCAsmBackend); 234 235 // Register the MCInstPrinter. 236 TargetRegistry::RegisterMCInstPrinter(TheSystemZTarget, 237 createSystemZMCInstPrinter); 238 } 239
