1 /* 2 * Copyright 2010 Jerome Glisse <glisse (at) freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26 #ifndef R600_PIPE_H 27 #define R600_PIPE_H 28 29 #include "r600_pipe_common.h" 30 #include "r600_cs.h" 31 #include "r600_public.h" 32 #include "pipe/p_defines.h" 33 34 #include "util/u_suballoc.h" 35 #include "util/list.h" 36 #include "util/u_transfer.h" 37 #include "util/u_memory.h" 38 39 #include "tgsi/tgsi_scan.h" 40 41 #define R600_NUM_ATOMS 56 42 43 #define R600_MAX_IMAGES 8 44 /* 45 * ranges reserved for images on evergreen 46 * first set for the immediate buffers, 47 * second for the actual resources for RESQ. 48 */ 49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160 50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168 51 52 /* read caches */ 53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0) 54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1) 55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2) 56 /* read-write caches */ 57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3) 58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4) 59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5) 60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6) 61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7) 62 /* engine synchronization */ 63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8) 64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9) 65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10) 66 67 /* the number of CS dwords for flushing and drawing */ 68 #define R600_MAX_FLUSH_CS_DWORDS 18 69 #define R600_MAX_DRAW_CS_DWORDS 58 70 #define R600_MAX_PFP_SYNC_ME_DWORDS 16 71 72 #define EG_MAX_ATOMIC_BUFFERS 8 73 74 #define R600_MAX_USER_CONST_BUFFERS 15 75 #define R600_MAX_DRIVER_CONST_BUFFERS 3 76 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS) 77 #define R600_MAX_HW_CONST_BUFFERS 16 78 79 /* start driver buffers after user buffers */ 80 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) 81 #define R600_UCP_SIZE (4*4*8) 82 #define R600_CS_BLOCK_GRID_SIZE (8 * 4) 83 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4) 84 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE) 85 86 /* 87 * We only access this buffer through vtx clauses hence it's fine to exist 88 * at index beyond 15. 89 */ 90 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) 91 /* 92 * Note GS doesn't use a constant buffer binding, just a resource index, 93 * so it's fine to have it exist at index beyond 15. I.e. it's not actually 94 * a const buffer, just a buffer resource. 95 */ 96 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) 97 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit 98 * of 16 const buffers. 99 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id. 100 * 101 * In order to support d3d 11 mandated minimum of 15 user const buffers 102 * we'd have to squash all use cases into one driver buffer. 103 */ 104 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4])) 105 106 /* HW stages */ 107 #define R600_HW_STAGE_PS 0 108 #define R600_HW_STAGE_VS 1 109 #define R600_HW_STAGE_GS 2 110 #define R600_HW_STAGE_ES 3 111 #define EG_HW_STAGE_LS 4 112 #define EG_HW_STAGE_HS 5 113 114 #define R600_NUM_HW_STAGES 4 115 #define EG_NUM_HW_STAGES 6 116 117 struct r600_context; 118 struct r600_bytecode; 119 union r600_shader_key; 120 121 /* This is an atom containing GPU commands that never change. 122 * This is supposed to be copied directly into the CS. */ 123 struct r600_command_buffer { 124 uint32_t *buf; 125 unsigned num_dw; 126 unsigned max_num_dw; 127 unsigned pkt_flags; 128 }; 129 130 struct r600_db_state { 131 struct r600_atom atom; 132 struct r600_surface *rsurf; 133 }; 134 135 struct r600_db_misc_state { 136 struct r600_atom atom; 137 bool occlusion_queries_disabled; 138 bool flush_depthstencil_through_cb; 139 bool flush_depth_inplace; 140 bool flush_stencil_inplace; 141 bool copy_depth, copy_stencil; 142 unsigned copy_sample; 143 unsigned log_samples; 144 unsigned db_shader_control; 145 bool htile_clear; 146 uint8_t ps_conservative_z; 147 }; 148 149 struct r600_cb_misc_state { 150 struct r600_atom atom; 151 unsigned cb_color_control; /* this comes from blend state */ 152 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 153 unsigned nr_cbufs; 154 unsigned nr_ps_color_outputs; 155 unsigned image_rat_enabled_mask; 156 unsigned buffer_rat_enabled_mask; 157 bool multiwrite; 158 bool dual_src_blend; 159 }; 160 161 struct r600_clip_misc_state { 162 struct r600_atom atom; 163 unsigned pa_cl_clip_cntl; /* from rasterizer */ 164 unsigned pa_cl_vs_out_cntl; /* from vertex shader */ 165 unsigned clip_plane_enable; /* from rasterizer */ 166 unsigned cc_dist_mask; /* from vertex shader */ 167 unsigned clip_dist_write; /* from vertex shader */ 168 unsigned cull_dist_write; /* from vertex shader */ 169 boolean clip_disable; /* from vertex shader */ 170 boolean vs_out_viewport; /* from vertex shader */ 171 }; 172 173 struct r600_alphatest_state { 174 struct r600_atom atom; 175 unsigned sx_alpha_test_control; /* this comes from dsa state */ 176 unsigned sx_alpha_ref; /* this comes from dsa state */ 177 bool bypass; 178 bool cb0_export_16bpc; /* from set_framebuffer_state */ 179 }; 180 181 struct r600_vgt_state { 182 struct r600_atom atom; 183 uint32_t vgt_multi_prim_ib_reset_en; 184 uint32_t vgt_multi_prim_ib_reset_indx; 185 uint32_t vgt_indx_offset; 186 bool last_draw_was_indirect; 187 }; 188 189 struct r600_blend_color { 190 struct r600_atom atom; 191 struct pipe_blend_color state; 192 }; 193 194 struct r600_clip_state { 195 struct r600_atom atom; 196 struct pipe_clip_state state; 197 }; 198 199 struct r600_cs_shader_state { 200 struct r600_atom atom; 201 unsigned kernel_index; 202 unsigned pc; 203 struct r600_pipe_compute *shader; 204 }; 205 206 struct r600_framebuffer { 207 struct r600_atom atom; 208 struct pipe_framebuffer_state state; 209 unsigned compressed_cb_mask; 210 unsigned nr_samples; 211 bool export_16bpc; 212 bool cb0_is_integer; 213 bool is_msaa_resolve; 214 bool dual_src_blend; 215 bool do_update_surf_dirtiness; 216 }; 217 218 struct r600_sample_mask { 219 struct r600_atom atom; 220 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 221 }; 222 223 struct r600_config_state { 224 struct r600_atom atom; 225 unsigned sq_gpr_resource_mgmt_1; 226 unsigned sq_gpr_resource_mgmt_2; 227 unsigned sq_gpr_resource_mgmt_3; 228 bool dyn_gpr_enabled; 229 }; 230 231 struct r600_stencil_ref 232 { 233 ubyte ref_value[2]; 234 ubyte valuemask[2]; 235 ubyte writemask[2]; 236 }; 237 238 struct r600_stencil_ref_state { 239 struct r600_atom atom; 240 struct r600_stencil_ref state; 241 struct pipe_stencil_ref pipe_state; 242 }; 243 244 struct r600_shader_stages_state { 245 struct r600_atom atom; 246 unsigned geom_enable; 247 }; 248 249 struct r600_gs_rings_state { 250 struct r600_atom atom; 251 unsigned enable; 252 struct pipe_constant_buffer esgs_ring; 253 struct pipe_constant_buffer gsvs_ring; 254 }; 255 256 /* This must start from 16. */ 257 /* features */ 258 #define DBG_NO_CP_DMA (1 << 30) 259 /* shader backend */ 260 #define DBG_NO_SB (1 << 21) 261 #define DBG_SB_CS (1 << 22) 262 #define DBG_SB_DRY_RUN (1 << 23) 263 #define DBG_SB_STAT (1 << 24) 264 #define DBG_SB_DUMP (1 << 25) 265 #define DBG_SB_NO_FALLBACK (1 << 26) 266 #define DBG_SB_DISASM (1 << 27) 267 #define DBG_SB_SAFEMATH (1 << 28) 268 269 struct r600_screen { 270 struct r600_common_screen b; 271 bool has_msaa; 272 bool has_compressed_msaa_texturing; 273 bool has_atomics; 274 275 /*for compute global memory binding, we allocate stuff here, instead of 276 * buffers. 277 * XXX: Not sure if this is the best place for global_pool. Also, 278 * it's not thread safe, so it won't work with multiple contexts. */ 279 struct compute_memory_pool *global_pool; 280 }; 281 282 struct r600_pipe_sampler_view { 283 struct pipe_sampler_view base; 284 struct list_head list; 285 struct r600_resource *tex_resource; 286 uint32_t tex_resource_words[8]; 287 bool skip_mip_address_reloc; 288 bool is_stencil_sampler; 289 }; 290 291 struct r600_rasterizer_state { 292 struct r600_command_buffer buffer; 293 boolean flatshade; 294 boolean two_side; 295 unsigned sprite_coord_enable; 296 unsigned clip_plane_enable; 297 unsigned pa_sc_line_stipple; 298 unsigned pa_cl_clip_cntl; 299 unsigned pa_su_sc_mode_cntl; 300 float offset_units; 301 float offset_scale; 302 bool offset_enable; 303 bool offset_units_unscaled; 304 bool scissor_enable; 305 bool multisample_enable; 306 bool clip_halfz; 307 bool rasterizer_discard; 308 }; 309 310 struct r600_poly_offset_state { 311 struct r600_atom atom; 312 enum pipe_format zs_format; 313 float offset_units; 314 float offset_scale; 315 bool offset_units_unscaled; 316 }; 317 318 struct r600_blend_state { 319 struct r600_command_buffer buffer; 320 struct r600_command_buffer buffer_no_blend; 321 unsigned cb_target_mask; 322 unsigned cb_color_control; 323 unsigned cb_color_control_no_blend; 324 bool dual_src_blend; 325 bool alpha_to_one; 326 }; 327 328 struct r600_dsa_state { 329 struct r600_command_buffer buffer; 330 unsigned alpha_ref; 331 ubyte valuemask[2]; 332 ubyte writemask[2]; 333 unsigned zwritemask; 334 unsigned sx_alpha_test_control; 335 }; 336 337 struct r600_pipe_shader; 338 339 struct r600_pipe_shader_selector { 340 struct r600_pipe_shader *current; 341 342 struct tgsi_token *tokens; 343 struct pipe_stream_output_info so; 344 struct tgsi_shader_info info; 345 346 unsigned num_shaders; 347 348 enum pipe_shader_type type; 349 350 /* geometry shader properties */ 351 enum pipe_prim_type gs_output_prim; 352 unsigned gs_max_out_vertices; 353 unsigned gs_num_invocations; 354 355 /* TCS/VS */ 356 uint64_t lds_patch_outputs_written_mask; 357 uint64_t lds_outputs_written_mask; 358 unsigned nr_ps_max_color_exports; 359 }; 360 361 struct r600_pipe_sampler_state { 362 uint32_t tex_sampler_words[3]; 363 union pipe_color_union border_color; 364 bool border_color_use; 365 bool seamless_cube_map; 366 }; 367 368 /* needed for blitter save */ 369 #define NUM_TEX_UNITS 16 370 371 struct r600_seamless_cube_map { 372 struct r600_atom atom; 373 bool enabled; 374 }; 375 376 struct r600_samplerview_state { 377 struct r600_atom atom; 378 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 379 uint32_t enabled_mask; 380 uint32_t dirty_mask; 381 uint32_t compressed_depthtex_mask; /* which textures are depth */ 382 uint32_t compressed_colortex_mask; 383 boolean dirty_buffer_constants; 384 }; 385 386 struct r600_sampler_states { 387 struct r600_atom atom; 388 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS]; 389 uint32_t enabled_mask; 390 uint32_t dirty_mask; 391 uint32_t has_bordercolor_mask; /* which states contain the border color */ 392 }; 393 394 struct r600_textures_info { 395 struct r600_samplerview_state views; 396 struct r600_sampler_states states; 397 bool is_array_sampler[NUM_TEX_UNITS]; 398 }; 399 400 struct r600_shader_driver_constants_info { 401 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */ 402 uint32_t *constants; 403 uint32_t alloc_size; 404 bool texture_const_dirty; 405 bool vs_ucp_dirty; 406 bool ps_sample_pos_dirty; 407 bool cs_block_grid_size_dirty; 408 bool tcs_default_levels_dirty; 409 }; 410 411 struct r600_constbuf_state 412 { 413 struct r600_atom atom; 414 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 415 uint32_t enabled_mask; 416 uint32_t dirty_mask; 417 }; 418 419 struct r600_vertexbuf_state 420 { 421 struct r600_atom atom; 422 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 423 uint32_t enabled_mask; /* non-NULL buffers */ 424 uint32_t dirty_mask; 425 }; 426 427 /* CSO (constant state object, in other words, immutable state). */ 428 struct r600_cso_state 429 { 430 struct r600_atom atom; 431 void *cso; /* e.g. r600_blend_state */ 432 struct r600_command_buffer *cb; 433 }; 434 435 struct r600_fetch_shader { 436 struct r600_resource *buffer; 437 unsigned offset; 438 }; 439 440 struct r600_shader_state { 441 struct r600_atom atom; 442 struct r600_pipe_shader *shader; 443 }; 444 445 struct r600_atomic_buffer_state { 446 uint32_t enabled_mask; 447 uint32_t dirty_mask; 448 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS]; 449 }; 450 451 struct r600_image_view { 452 struct pipe_image_view base; 453 uint32_t cb_color_base; 454 uint32_t cb_color_pitch; 455 uint32_t cb_color_slice; 456 uint32_t cb_color_view; 457 uint32_t cb_color_info; 458 uint32_t cb_color_attrib; 459 uint32_t cb_color_dim; 460 uint32_t cb_color_fmask; 461 uint32_t cb_color_fmask_slice; 462 uint32_t immed_resource_words[8]; 463 uint32_t resource_words[8]; 464 bool skip_mip_address_reloc; 465 uint32_t buf_size; 466 }; 467 468 struct r600_image_state { 469 struct r600_atom atom; 470 uint32_t enabled_mask; 471 uint32_t dirty_mask; 472 uint32_t compressed_depthtex_mask; 473 uint32_t compressed_colortex_mask; 474 boolean dirty_buffer_constants; 475 struct r600_image_view views[R600_MAX_IMAGES]; 476 }; 477 478 struct r600_context { 479 struct r600_common_context b; 480 struct r600_screen *screen; 481 struct blitter_context *blitter; 482 struct u_suballocator *allocator_fetch_shader; 483 484 /* Hardware info. */ 485 boolean has_vertex_cache; 486 unsigned default_gprs[EG_NUM_HW_STAGES]; 487 unsigned current_gprs[EG_NUM_HW_STAGES]; 488 unsigned r6xx_num_clause_temp_gprs; 489 490 /* Miscellaneous state objects. */ 491 void *custom_dsa_flush; 492 void *custom_blend_resolve; 493 void *custom_blend_decompress; 494 void *custom_blend_fastclear; 495 /* With rasterizer discard, there doesn't have to be a pixel shader. 496 * In that case, we bind this one: */ 497 void *dummy_pixel_shader; 498 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware 499 * bug where valid CMASK and FMASK are required to be present to avoid 500 * a hardlock in certain operations but aren't actually used 501 * for anything useful. */ 502 struct r600_resource *dummy_fmask; 503 struct r600_resource *dummy_cmask; 504 505 /* State binding slots are here. */ 506 struct r600_atom *atoms[R600_NUM_ATOMS]; 507 /* Dirty atom bitmask for fast tests */ 508 uint64_t dirty_atoms; 509 /* States for CS initialization. */ 510 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 511 /** Compute specific registers initializations. The start_cs_cmd atom 512 * must be emitted before start_compute_cs_cmd. */ 513 struct r600_command_buffer start_compute_cs_cmd; 514 /* Register states. */ 515 struct r600_alphatest_state alphatest_state; 516 struct r600_cso_state blend_state; 517 struct r600_blend_color blend_color; 518 struct r600_cb_misc_state cb_misc_state; 519 struct r600_clip_misc_state clip_misc_state; 520 struct r600_clip_state clip_state; 521 struct r600_db_misc_state db_misc_state; 522 struct r600_db_state db_state; 523 struct r600_cso_state dsa_state; 524 struct r600_framebuffer framebuffer; 525 struct r600_poly_offset_state poly_offset_state; 526 struct r600_cso_state rasterizer_state; 527 struct r600_sample_mask sample_mask; 528 struct r600_seamless_cube_map seamless_cube_map; 529 struct r600_config_state config_state; 530 struct r600_stencil_ref_state stencil_ref; 531 struct r600_vgt_state vgt_state; 532 struct r600_atomic_buffer_state atomic_buffer_state; 533 /* only have images on fragment shader */ 534 struct r600_image_state fragment_images; 535 struct r600_image_state compute_images; 536 struct r600_image_state fragment_buffers; 537 struct r600_image_state compute_buffers; 538 /* Shaders and shader resources. */ 539 struct r600_cso_state vertex_fetch_shader; 540 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES]; 541 struct r600_cs_shader_state cs_shader_state; 542 struct r600_shader_stages_state shader_stages; 543 struct r600_gs_rings_state gs_rings; 544 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; 545 struct r600_textures_info samplers[PIPE_SHADER_TYPES]; 546 547 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES]; 548 549 /** Vertex buffers for fetch shaders */ 550 struct r600_vertexbuf_state vertex_buffer_state; 551 /** Vertex buffers for compute shaders */ 552 struct r600_vertexbuf_state cs_vertex_buffer_state; 553 554 /* Additional context states. */ 555 unsigned compute_cb_target_mask; 556 struct r600_pipe_shader_selector *ps_shader; 557 struct r600_pipe_shader_selector *vs_shader; 558 struct r600_pipe_shader_selector *gs_shader; 559 560 struct r600_pipe_shader_selector *tcs_shader; 561 struct r600_pipe_shader_selector *tes_shader; 562 563 struct r600_pipe_shader_selector *fixed_func_tcs_shader; 564 565 struct r600_rasterizer_state *rasterizer; 566 bool alpha_to_one; 567 bool force_blend_disable; 568 bool gs_tri_strip_adj_fix; 569 boolean dual_src_blend; 570 unsigned zwritemask; 571 int ps_iter_samples; 572 573 /* The list of all texture buffer objects in this context. 574 * This list is walked when a buffer is invalidated/reallocated and 575 * the GPU addresses are updated. */ 576 struct list_head texture_buffers; 577 578 /* Last draw state (-1 = unset). */ 579 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */ 580 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ 581 enum pipe_prim_type last_rast_prim; 582 unsigned last_start_instance; 583 584 void *sb_context; 585 struct r600_isa *isa; 586 float sample_positions[4 * 16]; 587 float tess_state[8]; 588 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/ 589 struct r600_pipe_shader_selector *last_ls; 590 struct r600_pipe_shader_selector *last_tcs; 591 unsigned last_num_tcs_input_cp; 592 unsigned lds_alloc; 593 594 /* Debug state. */ 595 bool is_debug; 596 struct radeon_saved_cs last_gfx; 597 struct r600_resource *last_trace_buf; 598 struct r600_resource *trace_buf; 599 unsigned trace_id; 600 601 bool cmd_buf_is_compute; 602 struct pipe_resource *append_fence; 603 uint32_t append_fence_id; 604 }; 605 606 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, 607 struct r600_command_buffer *cb) 608 { 609 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); 610 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw); 611 cs->current.cdw += cb->num_dw; 612 } 613 614 static inline void r600_set_atom_dirty(struct r600_context *rctx, 615 struct r600_atom *atom, 616 bool dirty) 617 { 618 uint64_t mask; 619 620 assert(atom->id != 0); 621 assert(atom->id < sizeof(mask) * 8); 622 mask = 1ull << atom->id; 623 if (dirty) 624 rctx->dirty_atoms |= mask; 625 else 626 rctx->dirty_atoms &= ~mask; 627 } 628 629 static inline void r600_mark_atom_dirty(struct r600_context *rctx, 630 struct r600_atom *atom) 631 { 632 r600_set_atom_dirty(rctx, atom, true); 633 } 634 635 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 636 { 637 atom->emit(&rctx->b, atom); 638 r600_set_atom_dirty(rctx, atom, false); 639 } 640 641 static inline void r600_set_cso_state(struct r600_context *rctx, 642 struct r600_cso_state *state, void *cso) 643 { 644 state->cso = cso; 645 r600_set_atom_dirty(rctx, &state->atom, cso != NULL); 646 } 647 648 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx, 649 struct r600_cso_state *state, void *cso, 650 struct r600_command_buffer *cb) 651 { 652 state->cb = cb; 653 state->atom.num_dw = cb ? cb->num_dw : 0; 654 r600_set_cso_state(rctx, state, cso); 655 } 656 657 /* compute_memory_pool.c */ 658 struct compute_memory_pool; 659 void compute_memory_pool_delete(struct compute_memory_pool* pool); 660 struct compute_memory_pool* compute_memory_pool_new( 661 struct r600_screen *rscreen); 662 663 /* evergreen_state.c */ 664 struct pipe_sampler_view * 665 evergreen_create_sampler_view_custom(struct pipe_context *ctx, 666 struct pipe_resource *texture, 667 const struct pipe_sampler_view *state, 668 unsigned width0, unsigned height0, 669 unsigned force_level); 670 void evergreen_init_common_regs(struct r600_context *ctx, 671 struct r600_command_buffer *cb, 672 enum chip_class ctx_chip_class, 673 enum radeon_family ctx_family, 674 int ctx_drm_minor); 675 void cayman_init_common_regs(struct r600_command_buffer *cb, 676 enum chip_class ctx_chip_class, 677 enum radeon_family ctx_family, 678 int ctx_drm_minor); 679 680 void evergreen_init_state_functions(struct r600_context *rctx); 681 void evergreen_init_atom_start_cs(struct r600_context *rctx); 682 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 683 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 684 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 685 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 686 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 687 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 688 void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 689 void *evergreen_create_resolve_blend(struct r600_context *rctx); 690 void *evergreen_create_decompress_blend(struct r600_context *rctx); 691 void *evergreen_create_fastclear_blend(struct r600_context *rctx); 692 boolean evergreen_is_format_supported(struct pipe_screen *screen, 693 enum pipe_format format, 694 enum pipe_texture_target target, 695 unsigned sample_count, 696 unsigned usage); 697 void evergreen_init_color_surface(struct r600_context *rctx, 698 struct r600_surface *surf); 699 void evergreen_init_color_surface_rat(struct r600_context *rctx, 700 struct r600_surface *surf); 701 void evergreen_update_db_shader_control(struct r600_context * rctx); 702 bool evergreen_adjust_gprs(struct r600_context *rctx); 703 704 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a, 705 unsigned nr_cbufs); 706 /* r600_blit.c */ 707 void r600_init_blit_functions(struct r600_context *rctx); 708 void r600_decompress_depth_textures(struct r600_context *rctx, 709 struct r600_samplerview_state *textures); 710 void r600_decompress_depth_images(struct r600_context *rctx, 711 struct r600_image_state *images); 712 void r600_decompress_color_textures(struct r600_context *rctx, 713 struct r600_samplerview_state *textures); 714 void r600_decompress_color_images(struct r600_context *rctx, 715 struct r600_image_state *images); 716 void r600_resource_copy_region(struct pipe_context *ctx, 717 struct pipe_resource *dst, 718 unsigned dst_level, 719 unsigned dstx, unsigned dsty, unsigned dstz, 720 struct pipe_resource *src, 721 unsigned src_level, 722 const struct pipe_box *src_box); 723 724 /* r600_shader.c */ 725 int r600_pipe_shader_create(struct pipe_context *ctx, 726 struct r600_pipe_shader *shader, 727 union r600_shader_key key); 728 729 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 730 731 /* r600_state.c */ 732 struct pipe_sampler_view * 733 r600_create_sampler_view_custom(struct pipe_context *ctx, 734 struct pipe_resource *texture, 735 const struct pipe_sampler_view *state, 736 unsigned width_first_level, unsigned height_first_level); 737 void r600_init_state_functions(struct r600_context *rctx); 738 void r600_init_atom_start_cs(struct r600_context *rctx); 739 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 740 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 741 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 742 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); 743 void *r600_create_db_flush_dsa(struct r600_context *rctx); 744 void *r600_create_resolve_blend(struct r600_context *rctx); 745 void *r700_create_resolve_blend(struct r600_context *rctx); 746 void *r600_create_decompress_blend(struct r600_context *rctx); 747 bool r600_adjust_gprs(struct r600_context *rctx); 748 boolean r600_is_format_supported(struct pipe_screen *screen, 749 enum pipe_format format, 750 enum pipe_texture_target target, 751 unsigned sample_count, 752 unsigned usage); 753 void r600_update_db_shader_control(struct r600_context * rctx); 754 755 /* r600_hw_context.c */ 756 void r600_context_gfx_flush(void *context, unsigned flags, 757 struct pipe_fence_handle **fence); 758 void r600_begin_new_cs(struct r600_context *ctx); 759 void r600_flush_emit(struct r600_context *ctx); 760 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); 761 void r600_emit_pfp_sync_me(struct r600_context *rctx); 762 void r600_cp_dma_copy_buffer(struct r600_context *rctx, 763 struct pipe_resource *dst, uint64_t dst_offset, 764 struct pipe_resource *src, uint64_t src_offset, 765 unsigned size); 766 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, 767 struct pipe_resource *dst, uint64_t offset, 768 unsigned size, uint32_t clear_value, 769 enum r600_coherency coher); 770 void r600_dma_copy_buffer(struct r600_context *rctx, 771 struct pipe_resource *dst, 772 struct pipe_resource *src, 773 uint64_t dst_offset, 774 uint64_t src_offset, 775 uint64_t size); 776 777 /* 778 * evergreen_hw_context.c 779 */ 780 void evergreen_dma_copy_buffer(struct r600_context *rctx, 781 struct pipe_resource *dst, 782 struct pipe_resource *src, 783 uint64_t dst_offset, 784 uint64_t src_offset, 785 uint64_t size); 786 void evergreen_setup_tess_constants(struct r600_context *rctx, 787 const struct pipe_draw_info *info, 788 unsigned *num_patches); 789 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, 790 const struct pipe_draw_info *info, 791 unsigned num_patches); 792 void evergreen_set_ls_hs_config(struct r600_context *rctx, 793 struct radeon_winsys_cs *cs, 794 uint32_t ls_hs_config); 795 void evergreen_set_lds_alloc(struct r600_context *rctx, 796 struct radeon_winsys_cs *cs, 797 uint32_t lds_alloc); 798 799 /* r600_state_common.c */ 800 void r600_init_common_state_functions(struct r600_context *rctx); 801 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom); 802 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom); 803 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom); 804 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom); 805 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom); 806 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom); 807 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a); 808 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id); 809 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id, 810 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 811 unsigned num_dw); 812 void r600_vertex_buffers_dirty(struct r600_context *rctx); 813 void r600_sampler_views_dirty(struct r600_context *rctx, 814 struct r600_samplerview_state *state); 815 void r600_sampler_states_dirty(struct r600_context *rctx, 816 struct r600_sampler_states *state); 817 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 818 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx); 819 uint32_t r600_translate_stencil_op(int s_op); 820 uint32_t r600_translate_fill(uint32_t func); 821 unsigned r600_tex_wrap(unsigned wrap); 822 unsigned r600_tex_mipfilter(unsigned filter); 823 unsigned r600_tex_compare(unsigned compare); 824 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state); 825 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 826 const unsigned char *swizzle_view, 827 boolean vtx); 828 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 829 const unsigned char *swizzle_view, 830 uint32_t *word4_p, uint32_t *yuv_format_p, 831 bool do_endian_swap); 832 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format, 833 bool do_endian_swap); 834 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap); 835 836 /* r600_uvd.c */ 837 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context, 838 const struct pipe_video_codec *decoder); 839 840 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, 841 const struct pipe_video_buffer *tmpl); 842 843 /* 844 * Helpers for building command buffers 845 */ 846 847 #define PKT3_SET_CONFIG_REG 0x68 848 #define PKT3_SET_CONTEXT_REG 0x69 849 #define PKT3_SET_CTL_CONST 0x6F 850 #define PKT3_SET_LOOP_CONST 0x6C 851 852 #define R600_CONFIG_REG_OFFSET 0x08000 853 #define R600_CONTEXT_REG_OFFSET 0x28000 854 #define R600_CTL_CONST_OFFSET 0x3CFF0 855 #define R600_LOOP_CONST_OFFSET 0X0003E200 856 #define EG_LOOP_CONST_OFFSET 0x0003A200 857 858 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30) 859 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16) 860 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8) 861 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 862 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 863 864 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 865 866 /*Evergreen Compute packet3*/ 867 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 868 869 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value) 870 { 871 cb->buf[cb->num_dw++] = value; 872 } 873 874 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr) 875 { 876 assert(cb->num_dw+num <= cb->max_num_dw); 877 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0])); 878 cb->num_dw += num; 879 } 880 881 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 882 { 883 assert(reg < R600_CONTEXT_REG_OFFSET); 884 assert(cb->num_dw+2+num <= cb->max_num_dw); 885 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 886 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 887 } 888 889 /** 890 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 891 * shaders. 892 */ 893 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 894 { 895 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 896 assert(cb->num_dw+2+num <= cb->max_num_dw); 897 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 898 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 899 } 900 901 /** 902 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 903 * shaders. 904 */ 905 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 906 { 907 assert(reg >= R600_CTL_CONST_OFFSET); 908 assert(cb->num_dw+2+num <= cb->max_num_dw); 909 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 910 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 911 } 912 913 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 914 { 915 assert(reg >= R600_LOOP_CONST_OFFSET); 916 assert(cb->num_dw+2+num <= cb->max_num_dw); 917 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 918 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 919 } 920 921 /** 922 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 923 * shaders. 924 */ 925 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 926 { 927 assert(reg >= EG_LOOP_CONST_OFFSET); 928 assert(cb->num_dw+2+num <= cb->max_num_dw); 929 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 930 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 931 } 932 933 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 934 { 935 r600_store_config_reg_seq(cb, reg, 1); 936 r600_store_value(cb, value); 937 } 938 939 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 940 { 941 r600_store_context_reg_seq(cb, reg, 1); 942 r600_store_value(cb, value); 943 } 944 945 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 946 { 947 r600_store_ctl_const_seq(cb, reg, 1); 948 r600_store_value(cb, value); 949 } 950 951 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 952 { 953 r600_store_loop_const_seq(cb, reg, 1); 954 r600_store_value(cb, value); 955 } 956 957 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 958 { 959 eg_store_loop_const_seq(cb, reg, 1); 960 r600_store_value(cb, value); 961 } 962 963 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); 964 void r600_release_command_buffer(struct r600_command_buffer *cb); 965 966 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 967 { 968 radeon_set_context_reg_seq(cs, reg, num); 969 /* Set the compute bit on the packet header */ 970 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 971 } 972 973 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 974 { 975 assert(reg >= R600_CTL_CONST_OFFSET); 976 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); 977 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); 978 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2); 979 } 980 981 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 982 { 983 radeon_compute_set_context_reg_seq(cs, reg, 1); 984 radeon_emit(cs, value); 985 } 986 987 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) 988 { 989 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { 990 radeon_compute_set_context_reg(cs, reg, value); 991 } else { 992 radeon_set_context_reg(cs, reg, value); 993 } 994 } 995 996 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 997 { 998 radeon_set_ctl_const_seq(cs, reg, 1); 999 radeon_emit(cs, value); 1000 } 1001 1002 /* 1003 * common helpers 1004 */ 1005 1006 /* 12.4 fixed-point */ 1007 static inline unsigned r600_pack_float_12p4(float x) 1008 { 1009 return x <= 0 ? 0 : 1010 x >= 4096 ? 0xffff : x * 16; 1011 } 1012 1013 static inline unsigned r600_get_flush_flags(enum r600_coherency coher) 1014 { 1015 switch (coher) { 1016 default: 1017 case R600_COHERENCY_NONE: 1018 return 0; 1019 case R600_COHERENCY_SHADER: 1020 return R600_CONTEXT_INV_CONST_CACHE | 1021 R600_CONTEXT_INV_VERTEX_CACHE | 1022 R600_CONTEXT_INV_TEX_CACHE | 1023 R600_CONTEXT_STREAMOUT_FLUSH; 1024 case R600_COHERENCY_CB_META: 1025 return R600_CONTEXT_FLUSH_AND_INV_CB | 1026 R600_CONTEXT_FLUSH_AND_INV_CB_META; 1027 } 1028 } 1029 1030 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 1031 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1 1032 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2 1033 1034 unsigned r600_conv_prim_to_gs_out(unsigned mode); 1035 1036 void eg_trace_emit(struct r600_context *rctx); 1037 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f, 1038 unsigned flags); 1039 1040 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx, 1041 const struct tgsi_token *tokens, 1042 unsigned pipe_shader_type); 1043 int r600_shader_select(struct pipe_context *ctx, 1044 struct r600_pipe_shader_selector* sel, 1045 bool *dirty); 1046 1047 void r600_delete_shader_selector(struct pipe_context *ctx, 1048 struct r600_pipe_shader_selector *sel); 1049 1050 struct r600_shader_atomic; 1051 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, 1052 struct r600_pipe_shader *cs_shader, 1053 struct r600_shader_atomic *combined_atomics, 1054 uint8_t *atomic_used_mask_p); 1055 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, 1056 bool is_compute, 1057 struct r600_shader_atomic *combined_atomics, 1058 uint8_t *atomic_used_mask_p); 1059 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only); 1060 1061 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type); 1062 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only); 1063 #endif 1064
