1 //===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file declares the targeting of the RegisterBankInfo class for X86. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 15 #define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H 16 17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 18 19 #define GET_REGBANK_DECLARATIONS 20 #include "X86GenRegisterBank.inc" 21 22 namespace llvm { 23 24 class LLT; 25 26 class X86GenRegisterBankInfo : public RegisterBankInfo { 27 protected: 28 #define GET_TARGET_REGBANK_CLASS 29 #include "X86GenRegisterBank.inc" 30 #define GET_TARGET_REGBANK_INFO_CLASS 31 #include "X86GenRegisterBankInfo.def" 32 33 static RegisterBankInfo::PartialMapping PartMappings[]; 34 static RegisterBankInfo::ValueMapping ValMappings[]; 35 36 static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP); 37 static const RegisterBankInfo::ValueMapping * 38 getValueMapping(PartialMappingIdx Idx, unsigned NumOperands); 39 }; 40 41 class TargetRegisterInfo; 42 43 /// This class provides the information for the target register banks. 44 class X86RegisterBankInfo final : public X86GenRegisterBankInfo { 45 private: 46 /// Get an instruction mapping. 47 /// \return An InstructionMappings with a statically allocated 48 /// OperandsMapping. 49 const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI, 50 bool isFP) const; 51 52 /// Track the bank of each instruction operand(register) 53 static void 54 getInstrPartialMappingIdxs(const MachineInstr &MI, 55 const MachineRegisterInfo &MRI, const bool isFP, 56 SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx); 57 58 /// Construct the instruction ValueMapping from PartialMappingIdxs 59 /// \return true if mapping succeeded. 60 static bool 61 getInstrValueMapping(const MachineInstr &MI, 62 const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx, 63 SmallVectorImpl<const ValueMapping *> &OpdsMapping); 64 65 public: 66 X86RegisterBankInfo(const TargetRegisterInfo &TRI); 67 68 const RegisterBank & 69 getRegBankFromRegClass(const TargetRegisterClass &RC) const override; 70 71 InstructionMappings 72 getInstrAlternativeMappings(const MachineInstr &MI) const override; 73 74 /// See RegisterBankInfo::applyMapping. 75 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 76 77 const InstructionMapping & 78 getInstrMapping(const MachineInstr &MI) const override; 79 }; 80 81 } // namespace llvm 82 #endif 83
