1 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,-fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=NO-FP16 2 // RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-NO-FP16 %s < %t 3 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a,+fullfp16 < %s 2>%t | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 4 // RUN: FileCheck --check-prefix=STDERR --check-prefix=STDERR-FP16 %s < %t 5 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-v8.3a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=NO-V83A 6 7 8 // ==== FCMLA vector ==== 9 // Types 10 fcmla v0.4h, v1.4h, v2.4h, #0 11 // FP16: fcmla v0.4h, v1.4h, v2.4h, #0 // encoding: [0x20,0xc4,0x42,0x2e] 12 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 13 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 14 fcmla v0.8h, v1.8h, v2.8h, #0 15 // FP16: fcmla v0.8h, v1.8h, v2.8h, #0 // encoding: [0x20,0xc4,0x42,0x6e] 16 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 17 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 18 fcmla v0.2s, v1.2s, v2.2s, #0 19 // CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e] 20 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 21 fcmla v0.4s, v1.4s, v2.4s, #0 22 // CHECK: fcmla v0.4s, v1.4s, v2.4s, #0 // encoding: [0x20,0xc4,0x82,0x6e] 23 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 24 fcmla v0.2d, v1.2d, v2.2d, #0 25 // CHECK: fcmla v0.2d, v1.2d, v2.2d, #0 // encoding: [0x20,0xc4,0xc2,0x6e] 26 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 27 28 // Rotations 29 fcmla v0.2s, v1.2s, v2.2s, #0 30 // CHECK: fcmla v0.2s, v1.2s, v2.2s, #0 // encoding: [0x20,0xc4,0x82,0x2e] 31 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 32 fcmla v0.2s, v1.2s, v2.2s, #90 33 // CHECK: fcmla v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xcc,0x82,0x2e] 34 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 35 fcmla v0.2s, v1.2s, v2.2s, #180 36 // CHECK: fcmla v0.2s, v1.2s, v2.2s, #180 // encoding: [0x20,0xd4,0x82,0x2e] 37 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 38 fcmla v0.2s, v1.2s, v2.2s, #270 39 // CHECK: fcmla v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xdc,0x82,0x2e] 40 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 41 42 // Invalid rotations 43 fcmla v0.2s, v1.2s, v2.2s, #1 44 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 45 fcmla v0.2s, v1.2s, v2.2s, #360 46 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 47 fcmla v0.2s, v1.2s, v2.2s, #-90 48 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 49 50 // ==== FCADD vector ==== 51 // Types 52 fcadd v0.4h, v1.4h, v2.4h, #90 53 // FP16: fcadd v0.4h, v1.4h, v2.4h, #90 // encoding: [0x20,0xe4,0x42,0x2e] 54 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 55 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 56 fcadd v0.8h, v1.8h, v2.8h, #90 57 // FP16: fcadd v0.8h, v1.8h, v2.8h, #90 // encoding: [0x20,0xe4,0x42,0x6e] 58 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 59 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 60 fcadd v0.2s, v1.2s, v2.2s, #90 61 // CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e] 62 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 63 fcadd v0.4s, v1.4s, v2.4s, #90 64 // CHECK: fcadd v0.4s, v1.4s, v2.4s, #90 // encoding: [0x20,0xe4,0x82,0x6e] 65 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 66 fcadd v0.2d, v1.2d, v2.2d, #90 67 // CHECK: fcadd v0.2d, v1.2d, v2.2d, #90 // encoding: [0x20,0xe4,0xc2,0x6e] 68 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 69 70 // Rotations 71 fcadd v0.2s, v1.2s, v2.2s, #90 72 // CHECK: fcadd v0.2s, v1.2s, v2.2s, #90 // encoding: [0x20,0xe4,0x82,0x2e] 73 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 74 fcadd v0.2s, v1.2s, v2.2s, #270 75 // CHECK: fcadd v0.2s, v1.2s, v2.2s, #270 // encoding: [0x20,0xf4,0x82,0x2e] 76 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 77 78 // Invalid rotations 79 fcadd v0.2s, v1.2s, v2.2s, #1 80 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270. 81 fcadd v0.2s, v1.2s, v2.2s, #360 82 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270. 83 fcadd v0.2s, v1.2s, v2.2s, #-90 84 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270. 85 fcadd v0.2s, v1.2s, v2.2s, #0 86 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270. 87 fcadd v0.2s, v1.2s, v2.2s, #180 88 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270. 89 90 // ==== FCMLA indexed ==== 91 // Types 92 fcmla v0.4h, v1.4h, v2.h[0], #0 93 // FP16: fcmla v0.4h, v1.4h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x2f] 94 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 95 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 96 fcmla v0.8h, v1.8h, v2.h[0], #0 97 // FP16: fcmla v0.8h, v1.8h, v2.h[0], #0 // encoding: [0x20,0x10,0x42,0x6f] 98 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 99 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 100 fcmla v0.2s, v1.2s, v2.s[0], #0 101 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction 102 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction 103 fcmla v0.4s, v1.4s, v2.s[0], #0 104 // CHECK: fcmla v0.4s, v1.4s, v2.s[0], #0 // encoding: [0x20,0x10,0x82,0x6f] 105 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 106 fcmla v0.2d, v1.2d, v2.d[0], #0 107 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction 108 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: invalid operand for instruction 109 110 // Rotations 111 fcmla v0.4s, v1.4s, v2.s[0], #90 112 // CHECK: fcmla v0.4s, v1.4s, v2.s[0], #90 // encoding: [0x20,0x30,0x82,0x6f] 113 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 114 fcmla v0.4s, v1.4s, v2.s[0], #180 115 // CHECK: fcmla v0.4s, v1.4s, v2.s[0], #180 // encoding: [0x20,0x50,0x82,0x6f] 116 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 117 fcmla v0.4s, v1.4s, v2.s[0], #270 118 // CHECK: fcmla v0.4s, v1.4s, v2.s[0], #270 // encoding: [0x20,0x70,0x82,0x6f] 119 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 120 121 // Valid indices 122 fcmla v0.4h, v1.4h, v2.h[1], #0 123 // FP16: fcmla v0.4h, v1.4h, v2.h[1], #0 // encoding: [0x20,0x10,0x62,0x2f] 124 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 125 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 126 fcmla v0.8h, v1.8h, v2.h[3], #0 127 // FP16: fcmla v0.8h, v1.8h, v2.h[3], #0 // encoding: [0x20,0x18,0x62,0x6f] 128 // STDERR-NO-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: fullfp16 129 // NO-V83A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a 130 fcmla v0.4s, v1.4s, v2.s[1], #0 131 // CHECK: fcmla v0.4s, v1.4s, v2.s[1], #0 // encoding: [0x20,0x18,0x82,0x6f] 132 // NO-V83A: :[[@LINE-2]]:{{[0-9]*}}: error: instruction requires: armv8.3a 133 134 // Invalid indices 135 fcmla v0.4h, v1.4h, v2.h[2], #0 136 // STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction 137 // STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1]. 138 fcmla v0.8h, v1.8h, v2.h[4], #0 139 // STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction 140 // STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3]. 141 fcmla v0.4s, v1.4s, v2.s[2], #0 142 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1]. 143 144 // Invalid rotations 145 fcmla v0.4s, v1.4s, v2.s[0], #1 146 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 147 fcmla v0.4s, v1.4s, v2.s[0], #360 148 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 149 fcmla v0.4s, v1.4s, v2.s[0], #-90 150 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270. 151
