1 /* 2 * Device Tree Include file for Marvell Armada 385 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior (at) marvell.com> 7 * Gregory CLEMENT <gregory.clement (at) free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni (at) free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49 #include "armada-38x.dtsi" 50 51 / { 52 model = "Marvell Armada 385 family SoC"; 53 compatible = "marvell,armada385", "marvell,armada380"; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 enable-method = "marvell,armada-380-smp"; 59 60 cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a9"; 63 reg = <0>; 64 }; 65 cpu@1 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a9"; 68 reg = <1>; 69 }; 70 }; 71 72 soc { 73 internal-regs { 74 pinctrl@18000 { 75 compatible = "marvell,mv88f6820-pinctrl"; 76 }; 77 }; 78 79 pcie-controller { 80 compatible = "marvell,armada-370-pcie"; 81 status = "disabled"; 82 device_type = "pci"; 83 84 #address-cells = <3>; 85 #size-cells = <2>; 86 87 msi-parent = <&mpic>; 88 bus-range = <0x00 0xff>; 89 90 ranges = 91 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 92 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 93 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 94 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 95 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 96 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 97 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 98 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 99 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 100 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 101 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 102 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 103 104 /* 105 * This port can be either x4 or x1. When 106 * configured in x4 by the bootloader, then 107 * pcie@4,0 is not available. 108 */ 109 pcie@1,0 { 110 device_type = "pci"; 111 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 112 reg = <0x0800 0 0 0 0>; 113 #address-cells = <3>; 114 #size-cells = <2>; 115 #interrupt-cells = <1>; 116 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 117 0x81000000 0 0 0x81000000 0x1 0 1 0>; 118 interrupt-map-mask = <0 0 0 0>; 119 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 120 marvell,pcie-port = <0>; 121 marvell,pcie-lane = <0>; 122 clocks = <&gateclk 8>; 123 status = "disabled"; 124 }; 125 126 /* x1 port */ 127 pcie@2,0 { 128 device_type = "pci"; 129 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 130 reg = <0x1000 0 0 0 0>; 131 #address-cells = <3>; 132 #size-cells = <2>; 133 #interrupt-cells = <1>; 134 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 135 0x81000000 0 0 0x81000000 0x2 0 1 0>; 136 interrupt-map-mask = <0 0 0 0>; 137 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 138 marvell,pcie-port = <1>; 139 marvell,pcie-lane = <0>; 140 clocks = <&gateclk 5>; 141 status = "disabled"; 142 }; 143 144 /* x1 port */ 145 pcie@3,0 { 146 device_type = "pci"; 147 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 148 reg = <0x1800 0 0 0 0>; 149 #address-cells = <3>; 150 #size-cells = <2>; 151 #interrupt-cells = <1>; 152 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 153 0x81000000 0 0 0x81000000 0x3 0 1 0>; 154 interrupt-map-mask = <0 0 0 0>; 155 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 156 marvell,pcie-port = <2>; 157 marvell,pcie-lane = <0>; 158 clocks = <&gateclk 6>; 159 status = "disabled"; 160 }; 161 162 /* 163 * x1 port only available when pcie@1,0 is 164 * configured as a x1 port 165 */ 166 pcie@4,0 { 167 device_type = "pci"; 168 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 169 reg = <0x2000 0 0 0 0>; 170 #address-cells = <3>; 171 #size-cells = <2>; 172 #interrupt-cells = <1>; 173 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 174 0x81000000 0 0 0x81000000 0x4 0 1 0>; 175 interrupt-map-mask = <0 0 0 0>; 176 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 177 marvell,pcie-port = <3>; 178 marvell,pcie-lane = <0>; 179 clocks = <&gateclk 7>; 180 status = "disabled"; 181 }; 182 }; 183 }; 184 }; 185
