1 /* 2 * Copyright 2016 - Michael Kurz <michi.kurz (at) gmail.com> 3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha (at) st.com> 4 * 5 * Based on: 6 * stm32f469-disco.dts from Linux 7 * Copyright 2016 - Lee Jones <lee.jones (at) linaro.org> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This file is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 /dts-v1/; 49 #include "stm32f746.dtsi" 50 #include <dt-bindings/memory/stm32-sdram.h> 51 52 / { 53 model = "STMicroelectronics STM32F746-DISCO board"; 54 compatible = "st,stm32f746-disco", "st,stm32f746"; 55 56 chosen { 57 bootargs = "root=/dev/ram rdinit=/linuxrc"; 58 stdout-path = "serial0:115200n8"; 59 }; 60 61 memory { 62 reg = <0xC0000000 0x800000>; 63 }; 64 65 aliases { 66 serial0 = &usart1; 67 spi0 = &qspi; 68 mmc0 = &sdio; 69 /* Aliases for gpios so as to use sequence */ 70 gpio0 = &gpioa; 71 gpio1 = &gpiob; 72 gpio2 = &gpioc; 73 gpio3 = &gpiod; 74 gpio4 = &gpioe; 75 gpio5 = &gpiof; 76 gpio6 = &gpiog; 77 gpio7 = &gpioh; 78 gpio8 = &gpioi; 79 gpio9 = &gpioj; 80 gpio10 = &gpiok; 81 }; 82 83 led1 { 84 compatible = "st,led1"; 85 led-gpio = <&gpioi 1 0>; 86 }; 87 88 button1 { 89 compatible = "st,button1"; 90 button-gpio = <&gpioi 11 0>; 91 }; 92 93 backlight: backlight { 94 compatible = "gpio-backlight"; 95 gpios = <&gpiok 3 0>; 96 status = "okay"; 97 }; 98 99 panel-rgb@0 { 100 compatible = "simple-panel"; 101 backlight = <&backlight>; 102 enable-gpios = <&gpioi 12 0>; 103 status = "okay"; 104 105 display-timings { 106 timing@0 { 107 clock-frequency = <9000000>; 108 hactive = <480>; 109 vactive = <272>; 110 hfront-porch = <2>; 111 hback-porch = <2>; 112 hsync-len = <41>; 113 vfront-porch = <2>; 114 vback-porch = <2>; 115 vsync-len = <10>; 116 hsync-active = <0>; 117 vsync-active = <0>; 118 de-active = <0>; 119 pixelclk-active = <1>; 120 }; 121 }; 122 }; 123 }; 124 125 &clk_hse { 126 clock-frequency = <25000000>; 127 }; 128 129 &pinctrl { 130 usart1_pins_a: usart1@0 { 131 pins1 { 132 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 133 bias-disable; 134 drive-push-pull; 135 slew-rate = <2>; 136 }; 137 pins2 { 138 pinmux = <STM32F746_PB7_FUNC_USART1_RX>; 139 bias-disable; 140 }; 141 }; 142 143 ethernet_mii: mii@0 { 144 pins { 145 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 146 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 147 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 148 <STM32F746_PA2_FUNC_ETH_MDIO>, 149 <STM32F746_PC1_FUNC_ETH_MDC>, 150 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 151 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 152 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 153 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 154 slew-rate = <2>; 155 }; 156 }; 157 158 qspi_pins: qspi@0 { 159 pins { 160 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 161 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 162 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, 163 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, 164 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 165 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 166 slew-rate = <2>; 167 }; 168 }; 169 170 fmc_pins: fmc@0 { 171 pins { 172 pinmux = <STM32F746_PD10_FUNC_FMC_D15>, 173 <STM32F746_PD9_FUNC_FMC_D14>, 174 <STM32F746_PD8_FUNC_FMC_D13>, 175 <STM32F746_PE15_FUNC_FMC_D12>, 176 <STM32F746_PE14_FUNC_FMC_D11>, 177 <STM32F746_PE13_FUNC_FMC_D10>, 178 <STM32F746_PE12_FUNC_FMC_D9>, 179 <STM32F746_PE11_FUNC_FMC_D8>, 180 <STM32F746_PE10_FUNC_FMC_D7>, 181 <STM32F746_PE9_FUNC_FMC_D6>, 182 <STM32F746_PE8_FUNC_FMC_D5>, 183 <STM32F746_PE7_FUNC_FMC_D4>, 184 <STM32F746_PD1_FUNC_FMC_D3>, 185 <STM32F746_PD0_FUNC_FMC_D2>, 186 <STM32F746_PD15_FUNC_FMC_D1>, 187 <STM32F746_PD14_FUNC_FMC_D0>, 188 189 <STM32F746_PE1_FUNC_FMC_NBL1>, 190 <STM32F746_PE0_FUNC_FMC_NBL0>, 191 192 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, 193 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, 194 195 <STM32F746_PG1_FUNC_FMC_A11>, 196 <STM32F746_PG0_FUNC_FMC_A10>, 197 <STM32F746_PF15_FUNC_FMC_A9>, 198 <STM32F746_PF14_FUNC_FMC_A8>, 199 <STM32F746_PF13_FUNC_FMC_A7>, 200 <STM32F746_PF12_FUNC_FMC_A6>, 201 <STM32F746_PF5_FUNC_FMC_A5>, 202 <STM32F746_PF4_FUNC_FMC_A4>, 203 <STM32F746_PF3_FUNC_FMC_A3>, 204 <STM32F746_PF2_FUNC_FMC_A2>, 205 <STM32F746_PF1_FUNC_FMC_A1>, 206 <STM32F746_PF0_FUNC_FMC_A0>, 207 208 <STM32F746_PH3_FUNC_FMC_SDNE0>, 209 <STM32F746_PH5_FUNC_FMC_SDNWE>, 210 <STM32F746_PF11_FUNC_FMC_SDNRAS>, 211 <STM32F746_PG15_FUNC_FMC_SDNCAS>, 212 <STM32F746_PC3_FUNC_FMC_SDCKE0>, 213 <STM32F746_PG8_FUNC_FMC_SDCLK>; 214 slew-rate = <2>; 215 }; 216 }; 217 218 ltdc_pins: ltdc@0 { 219 pins { 220 pinmux = <STM32F746_PE4_FUNC_LCD_B0>, 221 <STM32F746_PG12_FUNC_LCD_B4>, 222 <STM32F746_PI9_FUNC_LCD_VSYNC>, 223 <STM32F746_PI10_FUNC_LCD_HSYNC>, 224 <STM32F746_PI14_FUNC_LCD_CLK>, 225 <STM32F746_PI15_FUNC_LCD_R0>, 226 <STM32F746_PJ0_FUNC_LCD_R1>, 227 <STM32F746_PJ1_FUNC_LCD_R2>, 228 <STM32F746_PJ2_FUNC_LCD_R3>, 229 <STM32F746_PJ3_FUNC_LCD_R4>, 230 <STM32F746_PJ4_FUNC_LCD_R5>, 231 <STM32F746_PJ5_FUNC_LCD_R6>, 232 <STM32F746_PJ6_FUNC_LCD_R7>, 233 <STM32F746_PJ7_FUNC_LCD_G0>, 234 <STM32F746_PJ8_FUNC_LCD_G1>, 235 <STM32F746_PJ9_FUNC_LCD_G2>, 236 <STM32F746_PJ10_FUNC_LCD_G3>, 237 <STM32F746_PJ11_FUNC_LCD_G4>, 238 <STM32F746_PJ13_FUNC_LCD_B1>, 239 <STM32F746_PJ14_FUNC_LCD_B2>, 240 <STM32F746_PJ15_FUNC_LCD_B3>, 241 <STM32F746_PK0_FUNC_LCD_G5>, 242 <STM32F746_PK1_FUNC_LCD_G6>, 243 <STM32F746_PK2_FUNC_LCD_G7>, 244 <STM32F746_PK4_FUNC_LCD_B5>, 245 <STM32F746_PK5_FUNC_LCD_B6>, 246 <STM32F746_PK6_FUNC_LCD_B7>, 247 <STM32F746_PK7_FUNC_LCD_DE>; 248 slew-rate = <2>; 249 }; 250 }; 251 }; 252 253 &usart1 { 254 pinctrl-0 = <&usart1_pins_a>; 255 pinctrl-names = "default"; 256 status = "okay"; 257 }; 258 259 &fmc { 260 pinctrl-0 = <&fmc_pins>; 261 pinctrl-names = "default"; 262 status = "okay"; 263 264 /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ 265 bank1: bank@0 { 266 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4 267 CAS_3 SDCLK_2 RD_BURST_EN 268 RD_PIPE_DL_0>; 269 st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 270 TRP_2 TRCD_2>; 271 /* refcount = (64msec/total_row_sdram)*freq - 20 */ 272 st,sdram-refcount = < 1542 >; 273 }; 274 }; 275 276 &mac { 277 status = "okay"; 278 pinctrl-0 = <ðernet_mii>; 279 phy-mode = "rmii"; 280 phy-handle = <&phy0>; 281 282 mdio0 { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 compatible = "snps,dwmac-mdio"; 286 phy0: ethernet-phy@0 { 287 reg = <0>; 288 }; 289 }; 290 }; 291 292 &qspi { 293 pinctrl-0 = <&qspi_pins>; 294 status = "okay"; 295 296 qflash0: n25q128a { 297 #address-cells = <1>; 298 #size-cells = <1>; 299 compatible = "micron,n25q128a13", "spi-flash"; 300 spi-max-frequency = <108000000>; 301 spi-tx-bus-width = <1>; 302 spi-rx-bus-width = <1>; 303 memory-map = <0x90000000 0x1000000>; 304 reg = <0>; 305 }; 306 }; 307 308 &sdio { 309 status = "okay"; 310 cd-gpios = <&gpioc 13 0>; 311 cd-inverted; 312 pinctrl-names = "default", "opendrain"; 313 pinctrl-0 = <&sdio_pins>; 314 pinctrl-1 = <&sdio_pins_od>; 315 bus-width = <4>; 316 max-frequency = <25000000>; 317 }; 318 319 <dc { 320 status = "okay"; 321 pinctrl-0 = <<dc_pins>; 322 }; 323
